MT9315 Zarlink Semiconductor, MT9315 Datasheet - Page 19

• Manufacturer Part Number: MT9315
• Description: Acoustic Echo CANceller
• Manufacturer: Zarlink Semiconductor

MT9315
18
Reset 6Dh
Reset 00h
Reset 00h
Power Up
Power Up
Power Up
22h Read
ACMUND
02h Read
Address:
Address:
Address:
20h R/W
HWLNG
NLPDC
NLPC
0h
1h
2h
3h
NBS
NBR
NB
NB
DT
DT
G0
G1
G2
G3
--
-
-
-
-
-
-
-
-
-
MSB
When high, the Narrowband signal has been detected in the Sin/Sout path and when low, the Narrowband signal has not
been detected in the Sin/Sout path
LOGICAL OR of the status bit NBS + NBR from LSR Register
When high the Double Talk is detected and when low, the Double talk is not detected
When high, the NLP is activated and when low the NLP is not activated
RESERVED.
When high, Howling is occurring in the loop and when low, no Howling is detected
When high, No active signal in the Rin/Rout path
RESERVED.
When high, a narrowband signal has been detected in the Receive (Rin) path. When low no narrowband signal is not
detected in the Rin path
This bit indicates a LOGICAL-OR of Stattus bits NBR + NBS ( from ASR Register)
When high, double-talk is detected and when low double-talk is not detected
When high, NLP is actiivated and when low NLP is not activated
RESERVED.
.
MSB
User Gain Control on the Rin/Rout path (Tolerance of gains: +/- 0.15 dB).
The hexadecimal number represents G3 to G0 value in the table below.
RESERVED
MSB
-24dB
-21dB
-18dB
-15dB
7
7
7
-
Gain Values for Receive Gain Control Register Bit G3 to G0 (RGC)
Acoustic Echo Canceller Status Register
-
-
Line Echo Canceller Status Register
6
6
6
ACMUND
-
4h
5h
6h
7h
-
5
5
Receive Gain Control Register
5
HWLNG
-
-12dB
-9 dB
-6 dB
-3 dB
-
4
4
4
-
-
-
3
3
3
Ah
Bh
8h
9h
NLPC
NLPDC
G3
(LSR)
(ASR)
2
+ 3 dB
+ 6 dB
2
+9 dB
2
0 dB
DT
(RGC)
(
G2
DT
* Do not write to this register
(
* Do not write to this register
1
Advance Information
1
1
NB
G1
NB
Ch
Dh
Eh
Fh
0
0
0
NBR
)
NBS
GO
+ 15 dB
+ 18 dB
+ 21 dB
+12 dB
)
LSB
LSB
LSB