MT9315 Zarlink Semiconductor, MT9315 Datasheet - Page 11

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MT9315

Manufacturer Part Number
MT9315
Description
Acoustic Echo CANceller
Manufacturer
Zarlink Semiconductor
Datasheet
MT9315
10
Note that the two ports are independent so that, for example, PORT1 can operate with 8 bit enable strobes and PORT2 can operate
with 16 bit enable strobes.
BCLK
PORT1
ENA1
Rin
Sout
PORT2
ENA2
Sin
Rout
The MT9315:
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to MT9315.
DATA 1
SCLK
CS
outputs = High impedance
inputs = don’t care
latches receive data on the rising edge of SCLK
outputs transmit data on the falling edge of SCLK
R/W
COMMAND/ADDRESS
A
0
A
1
Figure 8 - Serial Microport Timing for Intel Mode 0
A
2
A
3
A
4
1 bit - Read/Write
6 bits - Addressing Data
1 bit - Unused
A
5
Figure 7 - SSI Operation
X
8 or 16 bits
8 or 16 bits
8 or 16 bits
8 or 16 bits
D
0
D
DATA INPUT/OUTPUT
1
D
2
D
3
D
4
D
5
D
6
D
7
Advance Information

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