MT9041 Zarlink Semiconductor, MT9041 Datasheet - Page 8

• Manufacturer Part Number: MT9041
• Description: Single Reference Frequency Selectable Digital PLL With Multiple Clock Outputs For T1/E1 Trunk And Backplane Synchronization
• Manufacturer: Zarlink Semiconductor

Phase Continuity
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a
particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a
mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has
settled to a steady state.
In the case of the MT9041B, the output signal phase continuity is maintained to within ±5ns at the instance (over
one frame) of mode changes. The total phase shift may accumulate up to ±200ns over many frames. The rate of
change of the ±200ns phase shift is limited to a maximum phase slope of approximately 5ns/125us. This meets the
Bellcore GR-1244-CORE maximum phase slope requirement of 7.6ns/125us (81ns/1.326ms).
Phase Lock Time
This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal
and output signal are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
i) initial input to output phase difference
ii) initial input to output frequency difference
iii) synchronizer loop filter
iv) synchronizer limiter
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT9041B loop filter
and limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently,
phase lock time, which is not a standards requirement, may be longer than in other applications. See AC Electrical
Characteristics - Performance for maximum phase lock time.
MT9041B and Network Specifications
The MT9041B fully meets all applicable PLL requirements (intrinsic jitter, jitter tolerance, jitter transfer, frequency
accuracy, capture range and phase change slope) for the following specifications.
Applications
This section contains MT9041B application specific details for clock and crystal operation, reset operation and
power supply decoupling.
Master Clock
The MT9041B can use either a clock or crystal as the master timing source.
1. Bellcore GR-1244-CORE Issue 1, June 1995 for Stratum 4 Enhanced and Stratum 4
2. AT&T TR62411 (DS1) December 1990 for Stratum 4 Enhanced and Stratum 4
3. ANSI T1.101 (DS1) February 1994 for Stratum 4 Enhanced and Stratum 4
4. ETSI 300 011 (E1) April 1992 for Single Access and Multi Access
5. TBR 4 November 1995
6. TBR 12 December 1993
7. TBR 13 January 1996
8. ITU-T I.431 March 1993
Zarlink Semiconductor Inc.
MT9041B
8
Data Sheet