MT9041 Zarlink Semiconductor, MT9041 Datasheet - Page 6

• Manufacturer Part Number: MT9041
• Description: Single Reference Frequency Selectable Digital PLL With Multiple Clock Outputs For T1/E1 Trunk And Backplane Synchronization
• Manufacturer: Zarlink Semiconductor

MT9041B
Data Sheet
Normal Mode
Normal Mode is typically used when a slave clock source synchronized to the network is required.
In Normal Mode, the MT9041B provides timing (C1.5o, C2o, C3o, C4o, C8o and C16o) and frame synchronization
(F0o, F8o, F16o) signals, which are synchronized to reference input (REF). The input reference signal may have a
nominal frequency of 8kHz, 1.544MHz or 2.048MHz.
From a reset condition, the MT9041B will take up to 25 seconds for the output signal to be phase locked to the
reference.
The reference frequencies are selected by the frequency control pins FS2 and FS1 as shown in Table 1.
Freerun Mode
Freerun Mode is typically used when a master clock source is required, or immediately following system power-up
before network synchronization is achieved.
In Freerun Mode, the MT9041B provides timing and synchronization signals which are based on the master clock
frequency (OSCi) only, and are not synchronized to the reference signal (REF).
The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a ±32ppm output clock is
required, the master clock must also be ±32ppm. See Applications - Crystal and Clock Oscillator sections.
MT9041B Measures of Performance
The following are some synchronizer performance indicators and their corresponding definitions.
Intrinsic Jitter
Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by
applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may
also be measured when the device is in a non-synchronizing mode, i.e. free running mode, by measuring the output
jitter of the device. Intrinsic jitter is usually measured with various bandlimiting filters depending on the applicable
standards.
Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock), in the
presence of large jitter magnitudes at various jitter frequencies applied to its reference. The applied jitter magnitude
and jitter frequency depends on the applicable standards.
Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
For the MT9041B, two internal elements determine the jitter attenuation. This includes the internal 1.9Hz low pass
loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to 5ns/125us.
Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the
maximum output phase slope will be limited (i.e., attenuated) to 5ns/125us.
The MT9041B has nine outputs with three possible input frequencies for a total of 27 possible jitter transfer
functions. However, the data sheet section on AC Electrical Characteristics - Jitter Transfer specifies transfer
values for only three cases, 8kHz to 8kHz, 1.544MHz to 1.544MHz and 2.048MHz to 2.048MHz. Since all outputs
are derived from the same signal, these transfer values apply to all outputs.
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