MT9040AN Zarlink Semiconductor, MT9040AN Datasheet - Page 5

• Manufacturer Part Number: MT9040AN
• Description: Description = Single Reference Frequency Selectable, 3.3V Digital PLL With Multiple Clock Outputs For Stratum 4 Applications ;; Package Type = Ssop ;; No. Of Pins = 48
• Manufacturer: Zarlink Semiconductor

Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four
reference frequency selections (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). This filter ensures that the network
jitter transfer requirements are met.
Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input
Impairment Circuit to set the mode of the DPLL. The two possible modes are Normal and Freerun.
Digitally Controlled Oscillator (DCO) - the DCO receives the filtered signal from the Loop Filter, and based on its
value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on
the state of the MT9040.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the input reference
sinal.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source.
Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical to
the line frequency), and the input phase offset is small, then the lock signal will be set high. For specific Lock
Indicator design recommendations, see the Applications - Lock Indicator section.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure
4. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1 Divider Circuit,
and a DS2 Divider Circuit to generate the required output signals.
Four tapped delay lines are used to generate 16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz signals.
The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and five frame pulse outputs. The
C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.
These outputs have a nominal 50% duty cycle.
The T1 Divider Circuit uses the 12.384MHz signal to generate the C1.5o clock by dividing the internal C12 clock
by eight. This output has a nominal 50% duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal
50% duty cycle.
Reference
Frequency Select MUX
Feedback Signal
Detector
Phase
from
Figure 3 - DPLL Block Diagram
Zarlink Semiconductor Inc.
Input Impairment Monitor
MT9040
State Select
State Machine
from
State Select
5
Loop Filter
from
Controlled
Oscillator
Digitally
Control
Circuit
Output Interface Circuit
DPLL Reference
to
Data Sheet