MT9040AN Zarlink Semiconductor, MT9040AN Datasheet

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MT9040AN

Manufacturer Part Number
MT9040AN
Description
Description = Single Reference Frequency Selectable, 3.3V Digital PLL With Multiple Clock Outputs For Stratum 4 Applications ;; Package Type = Ssop ;; No. Of Pins = 48
Manufacturer
Zarlink Semiconductor
Datasheet

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Features
Applications
Supports AT&T TR62411 and Bellcore GR-1244-
CORE and Stratum 4 timing for DS1 interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and
TBR 13 timing for E1 interfaces
Selectable 19.44 MHz, 1.544MHz, 2.048MHz or
8kHz input reference signals
Provides C1.5, C2, C4, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
Provides 5 different styles of 8 KHz framing
pulses
Attenuates wander from 1.9Hz
Fast lock mode
JTAG Boundary Scan
Synchronization and timing control for multitrunk
T1 and E1 systems
ST-BUS clock and frame pulse source
TRST
TMS
TDO
TCK
REF
TDI
OSCi
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Master Clock
1149.1a
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
IEEE
Control State Machine
MS
OSCo
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
RST
Figure 1 - Functional Block Diagram
IM
FLOCK
Zarlink Semiconductor Inc.
1
LOCK
Description
The MT9040 T1/E1 System Synchronizer contains a
digital phase-locked loop (DPLL), which provides timing
and synchronization signals for T1 and E1 primary rate
transmission links.
The MT9040 generates ST-BUS clock and framing
signals that are phase locked to either a 19.44 MHz,
2.048MHz, 1.544MHz, or 8kHz input reference.
The MT9040 is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE, Stratum 4; and ETSI ETS
300 011. It will meet the jitter/wander tolerance, jitter
transfer, intrinsic jitter, frequency accuracy and capture
range for these specifications.
Impairment
Monitor
DPLL
Input
Feedback
VDD
MT9040AN 48 pin SSOP
VSS
FS1
Ordering Information
Frequency
-40°C to +85°C
Interface
Output
Select
Circuit
MUX
FS2
T1/E1 Synchronizer
Data Sheet
November 2003
MT9040
C19o
C1.5o
C2o
C4o
C6o
C8o
C16o
F0o
F8o
F16o
RSP
TSP

Related parts for MT9040AN

MT9040AN Summary of contents

Page 1

... France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. MT9040AN 48 pin SSOP Description The MT9040 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links ...

Page 2

... TMS TCK RST 3 46 TRST TDI TDO REF 7 42 Vdd FS1 OSCo 40 9 OSCi FS2 10 MT9040AN 39 Vss IC 38 F16o F0o RSP 14 35 Vdd TSP F8o C1. Vdd 18 31 Vss ...

Page 3

... Frequency Select 1 (Input). See pin description for FS2. 44 TDO Test Serial Data Out (CMOS Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled. MT9040 Description 3 Zarlink Semiconductor Inc. Data Sheet ...

Page 4

... Loop Filter. The Frequency Select MUX allows the proper feedback signal to be externally selected (e.g., 8kHz, 1.544MHz, 2.048MHz or 19.44MHz). MT9040 Description . DD FS1 Input Frequency 0 0 19.44MHz 1 8kHz 1 0 1.544MHz 1 2.048MHz Table 1 - Input Frequency Selection 4 Zarlink Semiconductor Inc. Data Sheet ...

Page 5

... The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal 50% duty cycle. MT9040 Digitally Loop Filter Controlled Oscillator State Select Control from Circuit Input Impairment Monitor State Select from State Machine Figure 3 - DPLL Block Diagram 5 Zarlink Semiconductor Inc. Data Sheet DPLL Reference to Output Interface Circuit ...

Page 6

... Applications - Master Clock section. MT9040 T1 Divider C1.5o 12MHz Tapped Delay Line C2o E1 Divider C4o Tapped C8o Delay 16MHz C16o Line F0o F8o F16o Tapped Delay Line 12MHz DS2 Divider Tapped 19MHz Delay C19o Line 6 Zarlink Semiconductor Inc. Data Sheet RSP TSP C6o ...

Page 7

... In the MT9040, the intrinsic Jitter is limited to less than 0.02UI on the 2.048MHz and 1.544MHz clocks. MT9040 Mode 0 NORMAL 1 FREERUN Table 2 - Operating Modes and States ± 32ppm. See Applications - Crystal and Clock Oscillator sections. 7 Zarlink Semiconductor Inc. Data Sheet ± 32ppm output clock ...

Page 8

... For the MT9040, the Freerun accuracy is equal to the Master Clock (OSCi) accuracy. MT9040   – A ------ -   20 ×10 = InputT1   – 18 -------- -   20 × 2.5UI 1UIT1 × --------------------- - = OutputT1 ( ) 1UIE1 ( ) 644ns × ------------------- = OutputT1 = 3.3UI 488ns 8 Zarlink Semiconductor Inc. Data Sheet ...

Page 9

... This section contains MT9040 application specific details for clock and crystal operation, reset operation, power supply decoupling, and control operation. Master Clock The MT9040 can use either a clock or crystal as the master timing source. MT9040 ± 230 ppm minus the accuracy of the master clock 9 Zarlink Semiconductor Inc. Data Sheet ...

Page 10

... Figure 9. Crystal Oscillator - Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made crystal, resistor and capacitors is shown in Figure 6. MT9040 ± 32ppm. MT9040 +3.3V OSCi +3.3V 20MHz OUT GND 0.1uF OSCo No Connection Figure 5 - Clock Oscillator Circuit 10 Zarlink Semiconductor Inc. Data Sheet ...

Page 11

... Load Capacitance: 32pF Ω Maximum Series Resistance: 35 Approximate Drive Level: 1mW e.g., R1B23B32-20.0MHz ± (20ppm absolute, 6ppm 0C to 50C, 32pF, 25 MT9040 MT9040 OSCi 20MHz 1MΩ 56pF 39pF 3-50pF OSCo 100Ω 1uH Figure 6 - Crystal Oscillator Circuit Ω Zarlink Semiconductor Inc. Data Sheet ...

Page 12

... Capacitor’s discharge time Resistor value (3.3 MΩ Capacitor value (1µ Negative going threshold voltage of the T- Schmitt Trigger (2 3 MT9040 MT9040 +3.3V R 10kΩ RST R P 1kΩ C 10nF Figure 7 - Power-Up Reset Circuit 12 Zarlink Semiconductor Inc. Data Sheet is for protection P ...

Page 13

... Advanced Lock output will remain high positive pulse is detected on the LOCK output within 1.024 seconds, the Advanced LOCK output will go low. MT9040 MT9040 R=3.3M 74HC14 IN4148 + C=1µf Figure 8 - Time-constant Circuit Figure 9 - Digital Lock Pin Circuit 13 Zarlink Semiconductor Inc. Data Sheet 74HC14 LOCK ...

Page 14

... unless otherwise stated. SS Sym Min Max I 1.8 DDS 0.7V CIH DD V 0.3V CIL 2 0 Zarlink Semiconductor Inc. Data Sheet Min Max Units -0.3 7.0 V -0 °C -55 125 200 mW Max Units 3.6 V °C 85 Units Conditions/Notes mA Outputs unloaded mA Outputs unloaded V V µ ...

Page 15

... Sym Timing Reference Points t 15 Zarlink Semiconductor Inc. Data Sheet Conditions/ Max Units Notes† +0 ppm 4-8 +32 ppm 4-8 +100 ppm 4-8 +230 ppm 1-3,5-8 +198 ppm 1-3,5-8 +130 ppm ...

Page 16

... C15W t C6W t C2W t C4W t C8W t C16WL t TSPW t RSPW t C19WH t C19WL t F0WL t F8WH t F16WL t ORF Zarlink Semiconductor Inc. Data Sheet Min Max Units 100 - 337 363 ns 222 238 111 130 - -45 -25 ns ...

Page 17

... C15W t C6W t C2W t C4W t C8W t C16WL t TSPW t RSPW t C19WH t C19WL t F0WL t F8WH t F16WL t ORF Zarlink Semiconductor Inc. Data Sheet Min Max Units 100 - 337 363 ns 222 238 111 130 - -45 -25 ns ...

Page 18

... REF 19.44MHz F8o NOTES: 1. Input to output delay values are valid after a RST with no further state changes Figure 11 - Input to Output Timing (Normal Mode) MT9040 R15D R2D R19D Zarlink Semiconductor Inc. Data Sheet t R8D ...

Page 19

... TSP MT9040 t F0WL t F16WL t F16S t C4W t C2W t C6W t C15W t C19WH Figure 12 - Output Timing 1 t RSPD t t TSPW RSPW t TSPD Figure 13 - Output Timing 2 19 Zarlink Semiconductor Inc. Data Sheet t F8WH F0D F16H t C16D C8D C4D C2D V ...

Page 20

... S H Sym Max 0.0002 0.0002 0.0002 0.030 0.040 0.120 0.080 0.104 0.104 0.0002 0.0002 0.27 Sym Min Max 0.015 0.010 0.010 0.005 20 Zarlink Semiconductor Inc. Data Sheet Units Conditions/Notes† UIpp 1-12,19-22,26 UIpp 1-12,19-22,26 UIpp 1-12,19-22,26 UIpp 1-12,19-22,27 UIpp 1-12,19-22,28 UIpp 1-12,19-22,29 UIpp 1-12,19-22,30 UIpp 1-12,19-22,31 UIpp 1-12,19-22,32 ...

Page 21

... Sym Min Max Units Zarlink Semiconductor Inc. Data Sheet Conditions/Notes† 1-12,19-22,28 1-12,19-22,28 1-12,19-22,28 1-12,19-22,28 Conditions/Notes† 1,3,7-12, 19-20, 22, 26, 34 1,3,7-12, 19-20, 22, 26, 34 1,3,7-12, 19-20, 22, 26, 34 1,3,7-12, 19-20, 22, 26, 34 1,3,7-12, 19-20, 22, 26, 34 1,3,7-12, 19-20, 22, 26, 34 Conditions/Notes† 1,4,7-12, 19-20,22,27,34 1,4,7-12, 19-20,22,27,34 1,4,7-12, 19-20,22,27,34 1,4,7-12, 19-20,22,27,34 1,4,7-12, 19-20,22,27,34 1,4,7-12, 19-20,22,27,34 1,4,7-12, 19-20,22,27,34 ...

Page 22

... Jitter at output for 100kHz@0.20UIpp input with 40Hz to 100kHz filter 14 † See "Notes" following AC Electrical Characteristics tables. MT9040 Sym Min Max Units 2.9 UIpp 0.09 UIpp 1.3 UIpp 0.10 UIpp 0.80 UIpp 0.10 UIpp 0.40 UIpp 0.10 UIpp 0.06 UIpp 0.05 UIpp 0.04 UIpp 0.03 UIpp 0.04 UIpp 0.02 UIpp 22 Zarlink Semiconductor Inc. Data Sheet Conditions/Notes† 1,5,7-12,19-20, 22,28,34 1,5,7-12,19-20, 22,28,35 1,5,7-12,19-20, 22,28,34 1,5,7-12,19-20, 22,28,35 1,5,7-12,19-20, 22,28,34 1,5,7-12,19-20, 22,28,35 1,5,7-12,19-20, 22,28,34 1,5,7-12,19-20, 22,28,35 1,5,7-12,19-20, 22,28,34 1,5,7-12,19-20, 22,28,35 1,5,7-12,19-20, 22,28,34 1,5,7-12,19-20, 22,28,35 1,5,7-12,19-20, 22,28,34 1,5,7-12,19-20, 22,28,33 ...

Page 23

... See "Notes" following AC Electrical Characteristics tables. MT9040 Sym Min Max Units 0.80 UIpp 1,3,7 -12,19-20,22-24,26 0.70 UIpp 1,3,7 -12,19-20,22-24,26 0.60 UIpp 1,3,7 -12,19-20,22-24,26 0.20 UIpp 1,3,7 -12,19-20,22-24,26 0.15 UIpp 1,3,7 -12,19-20,22-24,26 0.08 UIpp 1,3,7 -12,19-20,22-24,26 0.02 UIpp 1,3,7 -12,19-20,22-24,26 0.01 UIpp 1,3,7 -12,19-20,22-24,26 Sym Min Max Units 150 UIpp 140 UIpp 130 UIpp 35 UIpp 25 UIpp 15 UIpp 4 UIpp 1 UIpp 0.5 UIpp 23 Zarlink Semiconductor Inc. Data Sheet Conditions/Notes† Conditions/Notes† 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 1,4,7-12,19-20,22-24,27 ...

Page 24

... Max Units 150 140 130 Sym Min Max -0 -32 +32 -100 +100 40 ± 0ppm. ± 32ppm. ± 100ppm. 24 Zarlink Semiconductor Inc. Data Sheet Conditions/Notes† UIpp 1,5,7 -12,19-20,22-24,28 UIpp 1,5,7 -12,19-20,22-24,28 UIpp 1,5,7 -12,19-20,22-24,28 UIpp 1,5,7 -12,19-20,22-24,28 UIpp 1,5,7 -12,19-20,22-24,28 UIpp 1,5,7 -12,19-20,22-24,28 UIpp 1,5,7 -12,19-20,22-24,28 UIpp 1,5,7 -12,19-20,22-24,28 UIpp 1,5,7 -12,19-20,22-24,28 Units Conditions/Notes† +0 ppm 13,16 ppm ...

Page 25

... No filter. 35. 40Hz to 100kHz bandpass filter. 36. With respect to reference input signal frequency. 37. After a RST. 38. Master clock duty cycle 40% to 60%. MT9040 25 Zarlink Semiconductor Inc. Data Sheet ...

Page 26

... Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...

Page 27

... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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