STM8S105XX STMicroelectronics, STM8S105XX Datasheet - Page 45

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STM8S105XX

Manufacturer Part Number
STM8S105XX
Description
(STM8S103XX / STM8S105XX) STM8S 8-bit MCU
Manufacturer
STMicroelectronics
Datasheet
STM8S103xx, STM8S105xx
Figure 27. Typical NRST pull-up resistance R
Figure 28. Typical NRST pull-up current I
The reset network shown in
must ensure that the level on the NRST pin can go below the V
Table
Figure 29. Recommended reset pin protection
External
14. Otherwise the reset is not taken into account internally.
circuit
reset
60
55
50
45
40
35
30
140
120
100
80
60
40
20
2.5
0
0
0.01µF
3
Figure 29
1
NRST
3.5
protects the device against parasitic resets. The user
2
V
DD
4
R
PU
V
pu
V
DD
DD
vs V
3
[V]
[V]
PU
4.5
DD
vs V
@ 4 temperatures
4
Filter
DD
5
@ 4 temperatures
IL
Internal reset
Electrical characteristics
max. level specified in
5
5.5
www.DataSheet4U.com
-40°C
25°C
85°C
125°C
-40°C
25°C
85°C
125°C
6
6
STM8
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