LPC2925 NXP Semiconductors, LPC2925 Datasheet - Page 41

• Manufacturer Part Number: LPC2925
• Description: (LPC2921 - LPC2925) ARM9 microcontroller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2921_2923_2925_0
Preliminary data sheet
Fig 8.
www.DataSheet4U.com
AHB2DTL
BRIDGE
Power, Clock, and Reset control Sub System (PCRSS) block diagram
6.15.1 Clock description
OSCILLATOR
LOW POWER
OSCILLATOR
REGISTERS
REGISTERS
EXTERNAL
The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the
AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and
PMU internal logic, see
BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is
derived from BASE_PCR_CLK and is always on in order to be able to wake up from
low-power modes.
CGU0/1
RING
RGU
POR
FDIV[6:0]
PLL
RESET OUTPUT
DELAY LOGIC
DEGLITCH/
INPUT
SYNC
Rev. 00.01 — 24 October 2008
Section
OUT11
OUT6
OUT0
OUT1
OUT5
OUT7
OUT9
CGU0
RGU
6.7.2. CLK_SYS_PCRSS is derived from
FDIV
PLL
ARM9 microcontroller with CAN and LIN
OUT0
OUT2
LPC2921/2923/2925
CGU1
RST_N (device pin)
reset from watchdog counter
WARM_RST
PCR_RST
COLD_RST
RGU_RST
POR_RST
AHB_RST
SCU_RST
REGISTERS
CONTROL
ENABLE
CLOCK
CLOCK
GATES
PMU
© NXP B.V. 2008. All rights reserved.
PMU
002aae249
wakeup_a
disable:
grant
request
master
branch
clocks
AHB
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