ADAV400 Analog Devices, ADAV400 Datasheet - Page 29

• Manufacturer Part Number: ADAV400
• Description: Audio Codec
• Manufacturer: Analog Devices

Table 30. RAM Modulo Control Register (8 Bits)
Register Address 0x1053
Register Bits
7:6
5:0
Table 31. Serial Output Control Register
Register Address 0x1054
Register Bits
15
14
13
12
11
10:9
8:7
6
5
4:2
1:0
Function
Reserved (set to 0)
RAM modulo size (1 LSB = 512 locations)
Function
Dither enable
TDM output mode
LRCLK polarity
BCLK polarity
Master/slave mode select
BCLK frequency (master mode)
LRCLK frame sync frequency (master mode)
Frame sync type
TDM enable
MSB position
Output Word length
0 = disabled
1 = enabled
0 = 8-channel TDM
1 = 16-channel TDM
0 = left low, right high
1 = left high, right low
0 = data changes on falling edge
1 = data changes on rising edge
0 = slave
1 = master
00 = 3.072 MHz (48 kHz)
01 = 6.144 MHz (96 kHz digital IO only)
10 = 12.288 MHz (192 kHz digital IO only)
11 = reserved
00 = 48 kHz
01 = 96 kHz
10 = 192 kHz
11 = reserved
0 = LRCLK
1 = pulse
0 = serial data out
1 = TDM out
000 = delay by 1
001 = delay by 0
010 = delay by 8
011 = delay by 12
100 = delay by 16
All others are reserved
00 = 24 bits
01 = 20 bits
10 = 16 bits
11 = 16 bits
Default = 0x0000
Default = 0x28
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Table 32. Serial Input Control Register (8 Bits)
Register Address 0x1055
Register Bits
7:6
5
4
3
2:0
Table 33. SRC Serial Port Control Register (8 Bits)
Register Address 0x1056
Register Bits
7
6:5
4
3
2:0
Function
Reserved (set to 0)
TDM input mode
LRCLK polarity
BCLK polarity
Serial input mode
Function
Reserved (set to 0)
SRC serial input port select
LRCLK polarity
BCLK polarity
Serial input mode
0 = 8-channel TDM
1 = 16-channel TDM
0 = left low, right high
1 = left high, right low
0 = data changes on falling edge
1 = data changes on rising edge
000 = I
001 = left-justified
010 = 8-channel TDM
011 = right-justified, 24 bits
100 = right-justified, 20 bits
101 = right-justified, 18 bits
110 = right-justified, 16 bits
All others are reserved
00 = SDIN3
01 = SDIN2
10 = SDIN1
11 = SDIN0
0 = left low, right high
1 = left high, right low
0 = data changes on falling edge
1 = data changes on rising edge
000 = I
001 = left-justified
010 = reserved
011 = right-justified, 24 bits
100 = right-justified, 20 bits
101 = right-justified, 18 bits
110 = right-justified, 16 bits
All others are reserved
2
2
S
S
Default = 0x00
Default = 0x00
ADAV400