EK43501-01 Peregrine Semiconductor Corp., EK43501-01 Datasheet - Page 8

• Manufacturer Part Number: EK43501-01
• Description: Specifications: Type: Attenuator ; Supplied Contents: Board ; For Use With/Related Products: PE43501 ; Frequency: 9kHz ~ 6GHz ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: Peregrine Semiconductor Corp.

Programming Options
Parallel/Serial Selection
Either a parallel or serial-addressable interface can
be used to control the PE43501. The P̅ / S bit
provides this selection, with P̅ / S=LOW selecting the
parallel interface and P̅ / S=HIGH selecting the serial-
addressable interface.
Parallel Mode Interface
The parallel interface consists of five CMOS-
compatible control lines that select the desired
attenuation state, as shown in Table 7.
The parallel interface timing requirements are
defined by Fig. 21 (Parallel Interface Timing
Diagram), Table 12 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
For latched-parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Fig. 21) to latch new attenuation state into
device.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
attenuation state control values will change device
state to new attenuation. Direct Mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
Serial-Addressable Interface
The serial-addressable interface is a 16-bit serial-in,
parallel-out shift register buffered by a transparent
latch. The 16-bits make up two words comprised of
8-bits each. The first word is the Attenuation Word,
which controls the state of the DSA. The second
word is the Address Word, which is compared to the
static (or programmed) logical states of the A0, A1
and A2 digital inputs. If there is an address match,
the DSA changes state; otherwise its current state
will remain unchanged. Fig. 20 illustrates an
example timing diagram for programming a state. It
is required that all parallel control inputs be
grounded when the DSA is used in serial-
addressable mode.
The serial-addressable interface is controlled using
three CMOS-compatible signals: Serial-In (SI),
Clock (CLK), and Latch Enable (LE). The SI and
CLK inputs allow data to be serially entered into the
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 13
shift register. Serial data is clocked in LSB first,
beginning with the Attenuation Word.
The shift register must be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data into the DSA. Address word and
attenuation word truth tables are listed in Table 8 &
Table 9, respectively. A programming example of the
serial-addressable register is illustrated in Table 10.
The serial-addressable timing diagram is illustrated
in Fig. 20.
Power-up Control Settings
The PE43501 will always initialize to the maximum
attenuation setting (7.75 dB) on power-up for both
the serial-addressable and latched-parallel modes of
operation and will remain in this setting until the user
latches in the next programming word. In direct-
parallel mode, the DSA can be preset to any state
within the 7.75 dB range by pre-setting the parallel
control pins prior to power-up. In this mode, there is
a 400-µs delay between the time the DSA is
powered-up to the time the desired state is
set. During this power-up delay, the device
attenuates to the maximum attenuation setting (7.75
dB) before defaulting to the user defined state. If the
control pins are left floating in this mode during
power-up, the device will default to the minimum
attenuation setting (insertion loss state).
Dynamic operation between serial-addressable and
parallel programming modes is possible.
If the DSA powers up in serial-addressable mode (P/
S = HIGH), all the parallel control inputs DI[4:0] must
be set to logic low. Prior to toggling to parallel mode,
the DSA must be programmed serially to ensure
D[7] is set to logic low.
If the DSA powers up in either latched or direct-
parallel mode, all parallel pins DI[4:0] must be set to
logic low prior to toggling to serial-addressable mode
(P̅ / S = HIGH), and held low until the DSA has been
programmed serially to ensure bit D[7] is set to logic
low.
The sequencing is only required once on power-
up. Once completed, the DSA may be toggled
between serial-addressable and parallel
programming modes at will.
Document No. 70-0251-05
│ UltraCMOS™ RFIC Solutions
Product Specification
PE43501