EK43501-01 Peregrine Semiconductor Corp., EK43501-01 Datasheet

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EK43501-01

Manufacturer Part Number
EK43501-01
Description
Specifications: Type: Attenuator ; Supplied Contents: Board ; For Use With/Related Products: PE43501 ; Frequency: 9kHz ~ 6GHz ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
Manufacturer
Peregrine Semiconductor Corp.
Datasheet
Product Description
The PE43501 is a HaRP™-enhanced, high linearity, 5-bit RF
Digital Step Attenuator (DSA). This highly versatile DSA
covers a 7.75 dB attenuation range in 0.25 dB steps. The
Peregrine 50Ω RF DSA provides a serial-addressable CMOS
control interface. It maintains high attenuation accuracy over
frequency and temperature and exhibits very low insertion loss
and low power consumption. Performance does not change
with V
Peregrine DSA is available in a 5x5 mm 32-lead QFN footprint.
The PE43501 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Package Type
32-lead 5x5x0.85 mm QFN Package
Figure 2. Functional Schematic Diagram
Document No. 70-0251-05 │ www.psemi.com
Parallel Control
Serial In
RF Input
DD
CLK
due to on-board regulator. This next generation
LE
5
A0
Switched Attenuator Array
Control Logic Interface
A1
A2
P/S
RF Output
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Features
50 Ω RF Digital Attenuator
5-bit, 7.75 dB, 9 kHz - 6.0 GHz
Product Specification
PE43501
HaRP™-enhanced UltraCMOS™ device
Attenuation: 0.25 dB steps to 7.75 dB
High Linearity: Typical +58 dBm IP3
3.3 V or 5.0 V Power Supply Voltage
Fast switch settling time
Programming Modes:
High-attenuation state @ power-up (PUP)
CMOS Compatible
No DC blocking capacitors required
Packaged in a 32-lead 5x5x0.85 mm QFN
Excellent low-frequency performance
Direct Parallel
Latched Parallel
Serial-Addressable: Program up to
eight addresses 000 - 111
Page 1 of 13

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EK43501-01 Summary of contents

Page 1

... Programming Modes: High-attenuation state @ power-up (PUP) CMOS Compatible No DC blocking capacitors required Packaged in a 32-lead 5x5x0.85 mm QFN RF Output A2 P/S ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Excellent low-frequency performance Direct Parallel Latched Parallel Serial-Addressable: Program up to eight addresses 000 - 111 Page ...

Page 2

... State 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 0 1000 2000 3000 Frequency (MHz) ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 3 5 Frequency 9 kHz ≤ 6 GHz 9 kHz < 4 GHz 4 GHz ≤ 6 GHz 4 GHz ≤ 6 GHz 4 GHz ≤ 6 GHz 9 kHz - 6 GHz All States 9 kHz - 6 GHz Input ...

Page 3

... Figure 12. Relative Phase vs. Frequency 85C ©2008-2009 Peregrine Semiconductor Corp. All rights reserved +25C 0dB 0.25dB 0.5dB 2dB 4dB 7.75dB Frequency (GHz) 7.75 dB State -40C 25C 85C ...

Page 4

... Attenuation Setting (dB) Figure 17. Input IP3 vs. Frequency 0dB 0.25dB 0.5dB 1000 2000 3000 4000 Frequency (MHz) ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page Figure 14. Attenuation Error vs. Attenuation 3000 MHz 1.5 1.0 0.5 0.0 -0.5 -1.0 -1 Figure 16. Attenuation Error vs. Attenuation +85C 1.5 1.0 0.5 ...

Page 5

... Switching rate is defined to be the speed at which the DSA can be toggled across attenuation states. Description Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page ...

Page 6

... Digital Input Leakage Note 1. Input leakage current per Control pin Figure 19. Maximum Power Handling Capability 1.0E+03 1.0E+04 1.0E+05 ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page Table 4. Absolute Maximum Ratings Max Units Symbol V V Power supply voltage DD 5 Voltage on any Digital input I µ ...

Page 7

... 7. Bits can either be set to logic high or logic low D5, D6 and D7 must be set to logic low Q10 ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Address Word ...

Page 8

... CMOS-compatible signals: Serial-In (SI), Clock (CLK), and Latch Enable (LE). The SI and CLK inputs allow data to be serially entered into the ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page shift register. Serial data is clocked in LSB first, beginning with the Attenuation Word. ...

Page 9

... Parallel data hold time DIH T Parallel/Serial setup time PSSU T Parallel/Serial hold time PSIH Digital register delay T PD (internal) Digital register delay T DIPD (internal, direct mode only) ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. T DIH T AIH T PSIH T LESU T LEPW T PD VALID Min Max ...

Page 10

... The user only must ensure that Latched- Parallel is selected in the software. For manual latched-parallel programming, the procedure is identical to direct-parallel except now ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page Figure 22. Evaluation Board Layout Peregrine Specification 101-0312 Note: Reference Fig. 23 for Evaluation Board Schematic the LE pin on the Serial header must be logic low as the parallel bits are applied ...

Page 11

... ADD A0_2 A2_1 A0 VDD A1_2 A1_1 A1 VDD A2_2 A0_1 A2 VDD HEADER3X3 OHM OHM J5 19 Z=50 Ohm SMA must also be grounded. SS ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. J2 VSS 1 2 CON2 C12 C11 100pf 0.1uF Page ...

Page 12

... Table 13. Ordering Information Order Code Part Marking PE43501MLI 43501 PE43501 G - 32QFN 5x5mm-75A PE43501MLI-Z 43501 PE43501 G – 32QFN 5x5mm-3000C EK43501-01 43501 ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page Tape Feed Direction YYWW = Date Code ZZZZZ = Last five digits of Lot Number Description ...

Page 13

... Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page ...

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