XC9500XL Xilinx Corp., XC9500XL Datasheet - Page 5

• Manufacturer Part Number: XC9500XL
• Description: XC9500XL 3.3 V CPLD Family
• Manufacturer: Xilinx Corp.

are initialized to the user-defined preload state (default to 0
if unspecified).
All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in
originates from either of three global clocks or a product
DS054 (v1.6) January 24, 2002
Preliminary Product Specification
54
R
Figure
4, the macrocell register clock
Figure 3: XC9500XL Macrocell Within Function Block
Allocator
Product
Term
Additional
Product
Terms
(from other
macrocells)
Additional
Product
Terms
(from other
macrocells)
Product Term Clock Enable
Product Term Clock
Product Term Reset
Product Term Set
Product Term OE
1
0
www.xilinx.com
1-800-255-7778
Set/Reset
Global
term clock. Both true and complement polarities of the
selected clock source can be used within each macrocell. A
GSR input is also provided to allow user registers to be set
to a user-defined state.
Global
Clocks
3
XC9500XL High-Performance CPLD Family
CE
D/T
R
S
Q
OUT
PTOE
To
FastCONNECTII
Switch Matrix
DS054_03_042101
To
I/O Blocks
5