XC9500XL Xilinx Corp., XC9500XL Datasheet - Page 14

• Manufacturer Part Number: XC9500XL
• Description: XC9500XL 3.3 V CPLD Family
• Manufacturer: Xilinx Corp.

XC9500XL High-Performance CPLD Family
Design Security
XC9500XL devices incorporate advanced data security fea-
tures which fully protect the programming data against
unauthorized reading or inadvertent device erasure/repro-
gramming.
available.
The read security bits can be set by the user to prevent the
internal programming pattern from being read or copied.
When set, they also inhibit further program operations but
allow device erase. Erasing the entire device is the only way
to reset the read security bit.
The write security bits provide added protection against
accidental device erasure or reprogramming when the
JTAG pins are subject to noise, such as during system
power-up. Once set, the write-protection may be deacti-
Low Power Mode
All XC9500XL devices offer a low-power mode for individual
macrocells or across all macrocells. This feature allows the
device power to be significantly reduced.
Each individual macrocell may be programmed in
low-power mode by the user. Performance-critical parts of
the application can remain in standard power mode, while
other parts of the application may be programmed for
low-power operation to reduce the overall power dissipation.
Macrocells programmed for low-power mode incur addi-
tional delay (t
register setup time. Product term clock to output and prod-
uct term output enable delays are unaffected by the macro-
cell power-setting.
14
Figure 14: System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
Table 3
LP
) in pin-to-pin combinatorial delay as well as
shows the four different security settings
(a)
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1-800-255-7778
vated when the device needs to be reprogrammed with a
valid pattern with a specific sequence of JTAG instructions.
Table 3: Data Security Options
Timing Model
The uniformity of the XC9500XL architecture allows a sim-
plified timing model for the entire device. The basic timing
model, shown in
that use the direct product terms only, with standard power
setting, and standard slew rate setting.
each of the key timing parameters is affected by the product
term allocator (if needed), low-power setting, and slew-lim-
ited setting.
The product term allocation time depends on the logic span
of the macrocell function, which is defined as one less than
the maximum number of allocators in the product term path.
If only direct product terms are used, then the logic span is
0. The example in
terms are available with a span of 1. In the case of
the 18 product term function has a span of 2.
Default
Set
Figure
Program/Erase
Program/Erase
Figure 6
Read Allowed
Read Allowed
(b)
Allowed
Allowed
Default
15, is valid for macrocell functions
Preliminary Product Specification
shows that up to 15 product
Read Security
DS054 (v1.6) January 24, 2002
Program Inhibited
X5902
Table 4
Program/Erase
Read Inhibited
Erase Allowed
Read Inhibited
Inhibited
Set
shows how
Figure
7,
R