XC9500XL Xilinx Corp., XC9500XL Datasheet - Page 13

• Manufacturer Part Number: XC9500XL
• Description: XC9500XL 3.3 V CPLD Family
• Manufacturer: Xilinx Corp.

The XC9500XL architecture provides for superior pin-lock-
ing characteristics with a combination of large number of
routing switches in the FastCONNECT II switch matrix, a
54-wide input Function Block, and flexible, bi-directional
product term allocation within each macrocell. These fea-
tures address design changes that require adding or chang-
ing internal routing, including additional signals into existing
equations, or increasing equation complexity, respectively.
In-System Programming
One or more XC9500XL devices can be daisy chained
together and programmed in-system via a standard 4-pin
JTAG protocol, as shown in
ming offers quick and efficient design iterations and elimi-
nates package handling. The Xilinx development system
provides the programming data sequence using a Xilinx
download cable, a third-party JTAG development system,
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence.
DS054 (v1.6) January 24, 2002
Preliminary Product Specification
PIN
0
V
CCIO
1.5V
Voltage
Output
Set to PIN
during valid user
operation
0
R
Figure 13: Bus-Hold Logic
Standard
Figure 12: Output Slew-Rate Control For (a) Rising and (b) Falling Outputs
T
SLEW
Drive to
V
Figure
CCIO
(a)
Level
14. In-system program-
Slew-Rate Limited
R
BH
DS054_13_042101
I/O
www.xilinx.com
1-800-255-7778
Time
For extensive design changes requiring higher logic capac-
ity than is available in the initially chosen device, the new
design may be able to fit into a larger pin-compatible device
using the same pin assignments. The same board may be
used with a higher density device without the expense of
board rework.
All I/Os are 3-stated and pulled high by the bus-hold cir-
cuitry during in-system programming. If a particular signal
must remain low during this time, then a pulldown resistor
may be added to the pin.
External Programming
XC9500XL devices can also be programmed by the Xilinx
HW-130 device programmer as well as third-party program-
mers. This provides the added flexibility of using pre-pro-
grammed devices during manufacturing, with an in-system
programmable option for future enhancements and design
changes.
Reliability and Endurance
All XC9500XL CPLDs provide a minimum endurance level
of 10,000 in-system program/erase cycles and a minimum
data retention of 20 years. Each device meets all functional,
performance, and data retention specifications within this
endurance limit.
IEEE 1149.1 Boundary-Scan (JTAG)
XC9500XL devices fully support IEEE 1149.1 bound-
ary-scan (JTAG). EXTEST, SAMPLE/PRELOAD, BYPASS,
USERCODE, INTEST, IDCODE, HIGHZ and CLAMP
instructions are supported in each device. Additional
instructions are included for in-system programming opera-
tions.
1.5V
Voltage
Output
0
XC9500XL High-Performance CPLD Family
T
SLEW
Standard
Slew-Rate Limited
(b)
DS054_12_042101
Time
13