AD1845 Analog Devices, AD1845 Datasheet - Page 27

no-image

AD1845

Manufacturer Part Number
AD1845
Description
Parallel-port 16-Bit Soundport Stereo Codec
Manufacturer
Analog Devices
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD1845JP
Manufacturer:
AD
Quantity:
5 510
Part Number:
AD1845JP
Manufacturer:
AD
Quantity:
1 000
Part Number:
AD1845JP
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD1845JP
Quantity:
13
Part Number:
AD1845JST
Manufacturer:
AD
Quantity:
2
Part Number:
AD1845JST
Manufacturer:
AD
Quantity:
164
Part Number:
AD1845JST
Manufacturer:
AD
Quantity:
1 000
Part Number:
AD1845JST
Manufacturer:
AD
Quantity:
1 000
Part Number:
AD1845JST
Manufacturer:
ADI
Quantity:
8 000
Part Number:
AD1845JST
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD1845JSTZ
Manufacturer:
SYNCMOS
Quantity:
12 000
Part Number:
AD1845TP
Quantity:
5
Part Number:
AD1845XP
Manufacturer:
ADI/亚德诺
Quantity:
20 000
REV. B
res
FREN
MIXPWD
DACPWD
ADCPWD
This register’s initial state after reset is “000x 0xxx.”
NOTE: Changing CFMT, CC/L, CS/M, requires the Mode Change Enable (MCE) state or setting CEN = 0.
res
CS/M
CC/L
CFMT
This register’s initial state after reset is “x000 xxxx.”
Power-Down Control Register (IXA3:0 = 27)
Capture Data Format Control Register (IXA3:0 = 28)
IXA3:0
IXA3:0
27
28
Reserved for future expansion. Always write zeros to these bits.
Frequency Select Register Enable. In MODE2, selecting this bit will turn on the Frequency Select Registers (see
indirect registers 22 and 23) and disable CFS2:0.
0
1
Mixer Power Down. The DAC and the output mixer are powered down, and the DAC sample clock is turned off.
DAC Power Down. The DAC is powered down and the DAC sample clock is turned off.
ADC Power Down. The ADC is powered down and the ADC sample clock is turned off.
Reserved for future expansion. Always write zeros to these bits.
Capture Stereo/Mono Select. Setting this bit determines how the captured audio data will be formatted. In the
Mono mode, valid information is captured on the “left” channel, and the “right” channel data is not valid.
0
1
Capture Companding/Linear Select. This bit is set to determine linear, -Law or A-Law companding. See Figure
12 for CFMT and CC/L bit settings that determine the audio data type capture format.
Capture Data Format. This bit is set to format the data being captured in MODE 2. See Figure 12 for CFMT
and CC/L bit settings that determine the capture audio data type format.
MIA3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ADCPWD
Data 7
Data 7
CFS Active.
Frequency Select Registers Active, CFS disabled.
Mono Format
Stereo Format
res
MIA2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DACPWD
Data 6
Data 6
CFMT
Figure 11. Mono Attenuation
MIXPWD
Data 5
Data 5
CC/L
MIA1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
–27–
Data 4
Data 4
CS/M
res
MIA0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data 3
Data 3
FREN
res
MONO Attenuation
–3.0 dB
–6.0 dB
–9.0 dB
–12.0 dB
–15.0 dB
–18.0 dB
–21.0 dB
–24.0 dB
–27.0 dB
–30.0 dB
–33.0 dB
–36.0 dB
–39.0 dB
–42.0 dB
–45.0 dB
0.0 dB
Data 2
Data 2
res
res
Data 1
Data 1
res
res
Data 0
Data 0
AD1845
res
res

Related parts for AD1845