AD1845 Analog Devices, AD1845 Datasheet - Page 23

• Manufacturer Part Number: AD1845
• Description: Parallel-port 16-Bit Soundport Stereo Codec
• Manufacturer: Analog Devices

REV. B
UB7:0
This register’s initial state after reset is “ 0000 0000.”
LB7:0
This register’s initial state after reset is “0000 0000.”
Expanded Modes (MODE2 = 1)
The following registers are enabled when the AD1845 is operating in MODE2 only.
DACZ
LMG4:0
TE
OL
This register’s initial state after reset is “0001 0001.”
res
RMG4:0
RMME
LMME
This register’s initial state after reset is “0001 000x.”
Upper Base Count Register (IXA3:0 = 14)
Lower Base Count Register (IXA3:0 = 15)
Alternate Feature Enable/Left MIC Input Control Register (IXA3:0 = 16)
MIC Mix Enable/Right MIC Input Control Register (IXA3:0 = 17)
IXA3:0
IXA3:0
IXA3:0
IXA3:0
14
15
16
17
Upper Base Count. This byte is the upper byte of the base count register containing the eight most significant bits
of the 16-bit base register. Reads from this register return the same value which was written. The current count
contained in the counters can not be read.
Lower Base Count. This byte is the lower byte of the base count register containing the eight least significant bits
of the 16-bit base register. Reads from this register return the same value which was written. The current count
contained in the counters cannot be read.
DAC Zero. When an underrun error occurs, this bit will force the DAC output to midscale.
0
1
Left MIC Gain. The least significant bit of this gain/attenuate select represents 1.5 dB. LMG4:0 = 0 produces
a +12 dB gain. LMG4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 dB.
See Figure 10.
Timer Enable. Setting this bit enables the 16-bit programmable timer (see Registers 20 and 21). When the timer
is enabled, the timer count is reloaded, and interrupts are generated at specified periods on the INT pin.
Output Level. This bit sets the analog output level. The line output level may be attenuated by 3 dB.
0
1
Reserved for future expansion. Always write zero to this bit.
Right MIC Gain. The least significant bit of this gain/attenuate select represents 1.5 dB. RMG4:0 = 0 produces a
+12 dB gain. RMG4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 dB.
See Figure 10.
Right MIC Mix Enable. Setting this bit enables the right microphone input to be mixed with the DAC output on
R_OUT.
Left MIC Mix Enable. Setting this bit enables the left microphone input to be mixed with the DAC output on
L_OUT.
LMME
Data 7
Data 7
Data 7
Data 7
UB7
LB7
Output previous valid sample
Output to midscale value
Full scale of 2.0 V p-p (–3 dB)
Full scale of 2.8 V p-p (0 dB)
OL
RMME
Data 6
Data 6
Data 6
Data 6
UB6
LB6
TE
Data 5
Data 5
Data 5
LMG4
Data 5
RMG4
UB5
LB5
–23–
Data 4
Data 4
Data 4
Data 4
RMG3
LMG3
UB4
LB4
Data 3
Data 3
Data 3
Data 3
RMG2
LMG2
UB3
LB3
Data 2
Data 2
Data 2
Data 2
RMG1
LMG1
UB2
LB2
Data 1
Data 1
Data 1
Data 1
RMG0
LMG0
UB1
LB1
Data 0
Data 0
Data 0
DACZ
Data 0
AD1845
UB0
LB0
res