AD1845 Analog Devices, AD1845 Datasheet - Page 26

• Manufacturer Part Number: AD1845
• Description: Parallel-port 16-Bit Soundport Stereo Codec
• Manufacturer: Analog Devices

AD1845
PU
PO
CO
CU
PI
CI
TI
res
This register’s initial state after reset is “x000 0000.”
V2:0
res
CID2:0
This register’s initial state after reset is “100x x000.”
MIA3:0
res
MOM
MIM
This register’s initial state after reset is “00xx 0011.”
Capture Playback Timer Register (IXA3:0 = 24)
Revision ID Register (IXA3:0 = 25)
Mono Control Registers (IXA3:0 = 26)
IXA3:0
IXA3:0
IXA3:0
24
25
26
Playback Underrun. This bit is set when the DAC runs out of data and a sample has been missed.
Playback Overrun. This bit is set when the host tries to write data into the FIFO and the write was ignored be-
cause the FIFO was full.
Capture Overrun. This bit is set when the ADC has a sample to load into the FIFO, and the data was ignored be-
cause the capture FIFO was full.
Capture Underrun. This bit is set when the host attempts to read from the capture FIFO when it is empty. Under
these circumstances, the last valid byte is sent to the host.
Playback Interrupt. This bit indicates that there is an interrupt pending from the playback DMA count registers.
Capture Interrupt. This bit indicates that there is an interrupt pending from the capture DMA count registers.
Timer Interrupt. This bit indicates that there is an interrupt pending from the timer count registers.
Reserved for future expansion. Always write zero to this bit.
Version Number. Indicates the version of the AD1845.
Reserved for future expansion. Always write zeros to these bits.
Chip ID Number.
Mono Input Attenuation. The least significant bit represents 3.0 dB attenuation. See Figure 11 to determine
the attenuation.
Reserved for future expansion. Always write zeros to these bits.
Mono Output Mute. M_OUT is muted by setting MOM to 1.
0
1
Mono Input Mute. M_IN is muted by setting MIM to 1.
0
1
Data 7
Data 7
Data 7
MIM
Mono output not muted
Mono output muted
Mono input not muted
Mono input muted
V2
res
Data 6
Data 6
Data 6
MOM
V1
TI
Data 5
Data 5
Data 5
V0
res
CI
–26–
Data 4
Data 4
Data 4
res
res
PI
Data 3
Data 3
Data 3
MIA3
CU
res
Data 2
Data 2
Data 2
CID2
MIA2
CO
Data 1
Data 1
Data 1
CID1
MIA1
PO
Data 0
Data 0
Data 0
MIA0
CID0
PU
REV. B