ADS7864YB Burr-Brown Corporation, ADS7864YB Datasheet - Page 14

• Manufacturer Part Number: ADS7864YB
• Description: 500kHz/ 12-Bit/ 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

At time t
signal all conversions and scheduled conversions are can-
celled. The data in the output registers are also cleared. With
a reset a running conversion gets interrupted and all chan-
nels go into the sample mode again.
At time t
clock edge (t
be converted next. As the reset signal occurred at t
conversion of channel B will be started with the next rising
edge of the clock after t
Within the next clock cycle (t
HOLDA (t
within one clock cycle, channel A will be converted first. So
as soon as the conversion of channel B is done, the conver-
sion of channel A will be initiated. After this second conver-
sion, channel C will be converted.
FIGURE 13. Example of Hold Signals.
FIGURE 14. Functionality Diagram of FIFO Registers.
RESET
A
BUSY
B
reg. 5
reg. 4
reg. 2
reg. 3
reg. 1
reg. 0
E
RD
(Figure 13) the ADS7864 resets. With the reset
a HOLDB signal occurs. With the next falling
) occur. If more than one hold signals get active
C
®
) the ADS7864 puts channel B into the loop to
ADS7864
C
.
t
0
empty
empty
empty
empty
empty
empty
C
HOLDC
CLOCK
HOLDA
HOLDB
RESET
to t
F
Conversion
Channel A
), HOLDC (t
t
A
t
1
empty
empty
empty
empty
ch A1
ch A0
D
A
) and
, the
t
B
Conversion
Channel B
14
t
t
2
C
empty
empty
empty
empty
empty
ch A1
The 16 bit output word has following structure:
Bit 15 shows if the FIFO is empty (low) or if it contains
channel information (high). Bit 12 to 14 contain the Channel
for the 12 bit data word (Bit 0 to 11). If the data is from
channel A0, then bits 14 to 12 are 000. The Channel bit
pattern is outlined in Table I (Channel Truth Table).
New data is always written into the next available register. At
t
the new data of the channels A0 and A1 are put into registers
0 and 1. On t
Therefore this data is dumped and A1 data is shifted to register
0. At t
B1. This data is written into the next available registers
(register 1 and 2). The new data of channel C0 and C1 at t
put on top (registers 3 and 4).
0
(see Figure 14), the reset deletes all the existing data. At t
t
Valid
Data
D
t
E
3
t
F
t
3
new data is available, this time from channel B0 and
empty
empty
empty
ch B1
ch B0
ch A1
3-Bit Channel
Information
2
the read process of channel A0 data is finished.
Conversion
Channel C
t
4
empty
ch C1
ch C0
ch B1
ch B0
ch A1
12-Bit Data Word
4
is
1