XR16L570 Exar Corporation, XR16L570 Datasheet - Page 9

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XR16L570

Manufacturer Part Number
XR16L570
Description
SMALLEST 1.62V TO 5.5V UART
Manufacturer
Exar Corporation
Datasheet

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xr
REV. 1.0.0
The L570 UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a
software bit (bit-7) in the MCR register. This bit selects the prescaler to divide the input external clock by a
factor of 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a
programmable divisor (via DLL and DLM registers) between 1 and (2
of the serial data rate. The sampling rate clock is used by the transmitter for data bit shifting and receiver for
data sampling. The BRG divisor defaults to the maximum baud rate (DLL = 0x01 and DLM = 0x00) upon power
up.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate.
sampling rate clock rate. When using a non-standard data rate external clock, the divisor value can be
calculated for DLL/DLM with the following equation.
2.9
Programmable Baud Rate Generator
F
IGURE
CLK
divisor (decimal) = (clock frequency / prescaler) / (serial data rate x 16)
Table 3
6. B
AUD
shows the standard data rates available with a 14.7456 MHz external clock at 16X
Buffer
R
Clock
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
ATE
G
ENERATOR AND
Divide by 4
Divide by 1
Prescaler
Prescaler
P
9
RESCALER
MCR Bit-7=0
MCR Bit-7=1
(default)
Baud Rate
Generator
DLL and DLM
Registers
Logic
16
-1) to obtain a 16X sampling rate clock
Rate Clock to
Transmitter
Sampling
16X
XR16L570

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