XR16L570 Exar Corporation, XR16L570 Datasheet - Page 29

• Manufacturer Part Number: XR16L570
• Description: SMALLEST 1.62V TO 5.5V UART
• Manufacturer: Exar Corporation

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REV. 1.0.0
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
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This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem
changes state. These bits may be used for general purpose inputs when they are not used with modem
signals.
MSR[0]: Delta CTS# Input Flag
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MSR[1]: Delta DSR# Input Flag
Since the 24-QFN package of the L570 does not have the DSR# modem input, this bit has functionality only in
internal loopback mode when the DSR bit (MSR[4]) can be controlled via the DTR bit (MCR[0]).
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MSR[2]: Delta RI# Input Flag
Since the 24-QFN package of the L570 does not have the RI# modem input, this bit has functionality only in
internal loopback mode when the RI bit (MSR[6]) can be controlled via the OP1# bit (MCR[2]).
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MSR[3]: Delta CD# Input Flag
Since the 24-QFN package of the L570 does not have the CD# modem input, this bit has functionality only in
internal loopback mode when the CD bit (MSR[7]) can be controlled via the OP2# bit (MCR[3]).
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MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A logic 1 on the CTS# pin will stop UART transmitter as soon as the current character
has finished transmission, and a logic 0 will resume data transmission. Normally MSR bit-4 bit is the
complement of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the
MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used.
4.10
Logic 0 = No FIFO error (default).
Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
Modem Status Register (MSR) - Read Only
SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
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XR16L570