CLIENT ST Microelectronics, Inc., CLIENT Datasheet - Page 26

• Manufacturer Part Number: CLIENT
• Description: STPC Client Datasheet / PC Compatible Embeded Microprocessor
• Manufacturer: ST Microelectronics, Inc.

UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER
Removed statement; “The direction can be controlled by a strap option or an internal register bit.”
The following changes have been made to the Pin Description Chapter from Revision 1.0 to Release 1.2.
26/61
Section
Section
2.2.13.
2.1.
2.2.1.
2.2.1.
2.2.6.
2.2.6.
Change
Added
Change
Replaced
Replaced
Replaced
Replaced
Replaced
“Note;
By setting signals ST[3:0] to the following value allows the STPC to be put
Tristate. This means the STPC is switched off and no signals are being driven.“
“internal” With “assimilated “
“The DRAM controller to execute the host transactions is also driven by this
clock”
With
“This clock drives the DRAM controller to execute the host transactions”
“AD[31:0] PCI Address/Data. This is the 32-bit multiplexed address and data
bus of the PCI. This bus is driven by the master during the address phase and
data phase of write transactions. It is driven by the target during data phase of
read transactions.”
With
“AD[31:0] PCI Address/Data. This is the 32-bit PCI multiplexed address and
data bus. This bus is driven by the master during the address phase and data
phase of write transactions. It is driven by the target during data phase of read
transactions.”
“IDE devices are connected to SA[19:8] directly and ISA bus is connected to
these pins through two LS245 transceivers. The OE of the transceivers are
connected to ISAOE
nals of the transceivers are connected to CPC and IDE DD bus and the B bus
signals are connected to ISA SA bus.”
With
“IDE devices are connected to SA[19:8] directly and the ISA bus is connected
to these pins through two LS245 transceivers. The transceiver OEs are con-
nected to ISAOE
signals are connected to the CPC and IDE DD busses and B bus signals are
connected to ISA SA bus.”
“For IDE devices, these signals are used as the DA[2:0] and are connected to
DA[2:0] of IDE devices directly or through a buffer. If the toggling of signals is to
be masked during ISA bus cycles, they can be externally ORed before being
connected to the IDE devices.”
With
“For IDE devices, these signals are used as the DA[2:0] and are connected di-
rectly or through a buffer to DA[2:0] of the IDE devices. If the toggling of signals
are to be masked during ISA bus cycles, they can be externally ORed before
being connected to the IDE devices.”
Text
Text
Issue 2.2 - October 13, 2000
#
and the DIR is connected to MASTER
#
and the DIR is connected to MASTER
#
. The transceiver bus
#
. The A bus sig-