CLIENT ST Microelectronics, Inc., CLIENT Datasheet - Page 13

• Manufacturer Part Number: CLIENT
• Description: STPC Client Datasheet / PC Compatible Embeded Microprocessor
• Manufacturer: ST Microelectronics, Inc.

Table 2-2. Definition of Signal Pins
RTCRW#* / DD[13]
RTCDS#* / DD[12]
SA[19:8]* / DD[11:0]
SA[7:0]
SD[15:0]*
ISA/IDE COMBINED CONTROL
IOCHRDY* / DIORDY
ISA CONTROL
ALE*
BHE#*
MEMR#*, MEMW#*
SMEMR#*, SMEMW#*
IOR#*, IOW#*
MASTER#*
MCS16#*, IOCS16#*
REF#*
AEN*
IOCHCK#*
ISAOE#*
GPIOCS#*
IDE CONTROL
PIRQ*
SIRQ*
PDRQ*
SDRQ*
PDACK#*
SDACK#*
PIOR#*
PIOW#*
SIOR#*
SIOW#*
IPC
IRQ_MUX[3:0]*
DREQ_MUX[1:0]*
DACK_ENC[2:0]*
TC*
MONITOR INTERFACE
RED, GREEN, BLUE
VSYNC*
HSYNC*
VREF_DAC
RSET
COMP
SCL / DDC[1]*
Note; * denotes theat the pin is V
Signal Name
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
5T
Compensation
(see
RTC Read/Write / Data Bus bit 13 (IDE)
RTC Data Strobe / Data Bus bit 12 (IDE)
Latched Address (ISA) / Data Bus (IDE)
Latched Address (IDE)
Data Bus (ISA)
I/O Channel Ready (ISA) - Busy/Ready (IDE)
Address Latch Enable
System Bus High Enable
Memory Read and Memory Write
System Memory Read and Memory Write
I/O Read and Write
Add On Card Owns Bus
Memory/IO Chip Select16
Refresh Cycle.
Address Enable
I/O Channel Check.
Bidirectional OE Control
General Purpose Chip Select
Primary Interrupt Request
Secondary Interrupt Request
Primary DMA Request
Secondary DMA Request
Primary DMA Acknowledge
Secondary DMA Acknowledge
Primary I/O Read
Primary I/O Write
Secondary I/O Read
Secondary I/O Write
Multiplexed Interrupt Request
Multiplexed DMA Request
DMA Acknowledge
ISA Terminal Count
Red, Green, Blue
Vertical Synchronization
Horizontal Synchronization
DAC Voltage reference
Resistor Set
I²C Interface - Clock / Can be used for VGA DDC[1] signal
Issue 2.2 - October 13, 2000
Section 4.
)
Description
PIN DESCRIPTION
Qty
16
16
1
1
1
4
1
1
1
2
2
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
2
3
1
3
1
1
1
1
1
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