MAX9879 Maxim Integrated Products, MAX9879 Datasheet - Page 24

• Manufacturer Part Number: MAX9879
• Description: Stereo Class D Audio Subsystem
• Manufacturer: Maxim Integrated Products

www.datasheet4u.com
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
1 = MAX9879 bypass switches are closed and the
0 = Bypass mode disabled.
This mode does not control headphone operation.
The MAX9879 features independent enables and input
selection for each speaker amplifier and the headphone
amplifier. See Table 6 for a detailed description of the
available modes. If the right speaker amplifier is disabled,
the stereo signals are automatically summed to mono for
the left output and vice-versa.
The MAX9879 features an I
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facil-
itate communication between the MAX9879 and the
master at clock rates up to 400kHz. Figure 6 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX9879 by transmitting the
SMBus is a trademark of Intel Corp.
24
Figure 6. 2-Wire Interface Timing Diagram
Table 6. Speaker/Headphone Modes
SDA
SCL
RSPKEN
LSPKEN
Class D amplifier is disabled.
HPEN
______________________________________________________________________________________
ENA
ENB
BIT
t
HD:STA
CONDITION
START
Enable bit for left speaker
Enable bit for right speaker
Enable bit for headphone amplifier
Enable bit for input A
Enable bit for input B
Output Mode Control Register
I
Speaker/Headphone Output Mode
2
t
LOW
C Interface Specification
t
R
DESCRIPTION
2
Bypass Mode (BYPASS)
t
t
SU:DAT
C/SMBus™-compatible,
HIGH
t
F
(_SPKEN/HPEN)
t
HD:DAT
t
SU:STA
START CONDITION
proper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) con-
dition and a STOP (P) condition. Each word transmitted
to the MAX9879 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX9879 transmits the proper slave address fol-
lowed by a series of nine SCL pulses. The MAX9879
transmits data on SDA in sync with the master-generat-
ed SCL pulses. The master acknowledges receipt of
each byte of data. Each read sequence is framed by a
START (S) or REPEATED START (Sr) condition, a not
acknowledge, and a STOP (P) condition. SDA operates
as both an input and an open-drain output. A pullup
resistor, typically greater than 500Ω, is required on
SDA. SCL operates only as an input. A pullup resistor,
typically greater than 500Ω, is required on SCL if there
are multiple masters on the bus, or if the single master
has an open-drain SCL output. Series resistors in line
with SDA and SCL are optional. Series resistors protect
the digital inputs of the MAX9879 from high voltage
spikes on the bus lines, and minimize crosstalk and
undershoot of the bus signals.
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section).
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START (S) condition is a high-to-low transition
on SDA with SCL high. A STOP (P) condition is a low-to-
high transition on SDA while SCL is high (Figure 7).
REPEATED
t
SU:STA
START and STOP Conditions
t
SU:STO
CONDITION
STOP
t
BUF
Bit Transfer
CONDITION
START