MAX9160EUI Maxim, MAX9160EUI Datasheet - Page 8

• Manufacturer Part Number: MAX9160EUI
• Description: LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver
• Manufacturer: Maxim

Figure 3. Transition Time and Propagation Delay Timing Diagram
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
The MAX9160 delay can be adjusted by connecting a
resistor from RSET to ground. See Typical Operating
Characteristics for a graph of delay vs. RSET.
Each bank of seven LVTTL/LVCMOS drivers is con-
trolled by an output enable. Outputs follow the selected
input when EN_ is high. Outputs are low (not high
impedance) when EN_ = low.
Power dissipation at high switching frequencies may
exceed the power dissipation capacity of the standard
TSSOP package (see the Supply Current vs. Frequency
graph in the Typical Operating Characteristics). An EP
version of the TSSOP package is available that dissi-
pates higher power. Also, a space-saving QFN pack-
age with EP is available. The EP must be soldered to
the PC board.
8
OUT_
_______________________________________________________________________________________
SE_IN
IN+
IN-
Power Dissipation and Package Type
Propagation Delay and RSET
20% V
CC
t
PLH
V
0V DIFFERENTIAL
CC
/2
Output Enables
t R
50% V
CC
80% V
CC
Bypass each supply pin with high-frequency surface-
mount ceramic 0.1µF and 0.001µF capacitors in paral-
lel as close to the device as possible, with the smaller
value capacitor closest to the device.
A four-layer PC board that provides separate power,
ground, input, and output signals is recommended.
Keep input and output signals separated to prevent
coupling.
TRANSISTOR COUNT: 756
PROCESS: CMOS
80% V
CC
t
PHL
V
0V DIFFERENTIAL
CC
/2
Chip Information
t F
Supply Bypassing
50% V
20% V
Board Layout
CC
CC
V
CC
0V
V OH
V OL