MAX9160EUI Maxim, MAX9160EUI Datasheet - Page 6

• Manufacturer Part Number: MAX9160EUI
• Description: LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver
• Manufacturer: Maxim

LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
6
(MAX9160 with RSET = 12kΩ ±1%, V
unless otherwise noted.)
10, 11, 14, 15,
3.0
2.5
2.0
1.5
1.0
_______________________________________________________________________________________
19, 25, 28
17, 18, 20
3, 12, 16,
4, 7, 13,
3.0
22, 29
TRANSITION TIME vs. SUPPLY VOLTAGE
QFN
1
2
5
6
8
9
3.1
SUPPLY VOLTAGE (V)
PIN
3.2
t
R
7, 10, 20, 26
13–16, 18,
t
3.3
F
6, 17, 23
TSSOP
19, 21
11
12
4
5
8
9
3.4
3.5
CC
3.6
= 3.3V, C
OUTB_
NAME
SE_IN
RSET
GND
ENB
V
SEL
IN+
IN-
CC
Typical Operating Characteristics (continued)
10
L
9
8
7
6
5
4
3
2
1
0
= 20pF, ENA = ENB = high, IV
5
LVCMOS/LVTTL Level Logic Input. SEL = high selects SE_IN. SEL = low or
open selects IN+, IN-. SEL is pulled to GND by an internal resistor.
LVCMOS/LVTTL Level Input. SE_IN is pulled to GND by an internal resistor.
Positive Supply Voltage. Bypass with 0.1µF and 0.001µF capacitors to ground.
Ground
Noninverting Input of Differential Input
Inverting Input of Differential Input
Connect a 12kΩ ±1% resistor to ground to decrease the minimum to maximum
IN+, IN- to OUT_ propagation delay.
LVCMOS/LVTTL Level Logic Input. When ENB = high, outputs OUTB_ are
enabled and follow the selected input. When ENB = low or open, outputs
OUTB_ are driven low. ENB is pulled to GND by an internal resistor.
Bank B LVCMOS/LVTTL Outputs
DIFFERENTIAL PROPAGATION DELAY
t
10
PLH
t
PHL
vs. RSET
RSET (kΩ)
15
ID
I = 0.2, V
20
FUNCTION
CM
300
250
200
150
100
50
0
= 1.2V, f
0
SUPPLY NOISE AMPLITUDE (mV
50
OUTPUT JITTER vs. 200kHz
SUPPLY NOISE AMPLITUDE
IN
Pin Description
= 125MHz, T
100
DIFFERENTIAL INPUT
150
200
A
= +25°C,
P-P
250
)
300