max9160euit Maxim Integrated Products, Inc., max9160euit Datasheet
max9160euit
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max9160euit Summary of contents
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Rev 0; 4/02 14 LVTTL/LVCMOS Output Clock Driver General Description The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock driver repeats the selected LVDS or LVTTL/LVCMOS input on two output banks. Each bank consists of seven LVTTL/LVCMOS series terminated outputs and a ...
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LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver ABSOLUTE MAXIMUM RATINGS V to GND ..............................................................-0.3V to +4V CC IN+, IN- to GND........................................................-0.3V to +4V SE_IN, EN_, SEL, RSET, OUT_ to GND ........-0. Output Short-Circuit Duration (OUT_) ...
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LVTTL/LVCMOS Output Clock Driver DC ELECTRICAL CHARACTERISTICS (continued) = 3.0V to 3.6V, ENA = ENB = high, RSET = 12kΩ ±1%, differential input voltage age 2. ...
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LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver AC ELECTRICAL CHARACTERISTICS (continued) = 20pF, ENA = ENB = high, SEL = high or low, RSET = 12kΩ ±1%, differential input voltage 3.0V to 3.6V, C ...
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LVTTL/LVCMOS Output Clock Driver (MAX9160 with RSET = 12kΩ ±1 unless otherwise noted.) SINGLE-ENDED PROPAGATION DELAY vs. SUPPLY VOLTAGE 4.0 3.5 t PHL 3.0 t 2.5 PLH 2.0 1.5 1.0 0.5 0 3.0 3.1 3.2 3.3 3.4 ...
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LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver (MAX9160 with RSET = 12kΩ ±1 3.3V unless otherwise noted.) TRANSITION TIME vs. SUPPLY VOLTAGE 3.0 t 2 1.5 1.0 3.0 3.1 ...
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LVTTL/LVCMOS Output Clock Driver PIN QFN TSSOP 21, 23, 24, 26 22, 24, 25, 27, 30 EP* *MAX9160EGJ and MAX9160AEUI IN2 COMPARATOR V - 0.3V CC IN+ R IN1 ...
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LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver SE_IN IN- 0V DIFFERENTIAL IN+ t PLH 20 OUT_ Figure 3. Transition Time and Propagation Delay Timing Diagram Propagation Delay and RSET The MAX9160 delay ...
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LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver ENA SEL RSET IN+ DELAY IN- MUX SE_IN ENB _______________________________________________________________________________________ Functional Diagram V CC OUTA[0: OUTB[0:6] 9 ...
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LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver CARD 1 ASIC 1 1 LVDS SYSTEM CLOCK TEST CLOCK SINGLE ENDED TOP VIEW SEL SE_IN V CC GND IN+ IN- GND RSET 10 ______________________________________________________________________________________ CARD 2 ASIC 14 FPGA ...
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LVTTL/LVCMOS Output Clock Driver (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) ______________________________________________________________________________________ LVDS or LVTTL/LVCMOS Input to Package Information 11 ...
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LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) 12 ______________________________________________________________________________________ Package Information (continued) ...
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LVTTL/LVCMOS Output Clock Driver (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry ...