MAX793 Maxim, MAX793 Datasheet - Page 7

• Manufacturer Part Number: MAX793
• Description: 3.0V/3.3V Adjustable Microprocessor Supervisory Circuits
• Manufacturer: Maxim

______________________________________________________________Pin Description
MAX793/
MAX794
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
PIN
MAX795
—
—
—
—
—
—
—
—
1
2
3
4
5
6
7
8
_______________________________________________________________________________________
(MAX793)
(MAX794)
RESET IN
LOWLINE
BATT OK
BATT ON
CE OUT
3.0V/3.3V Adjustable Microprocessor
RESET
RESET
NAME
CE IN
WDO
BATT
GND
OUT
PFO
V
WDI
PFI
MR
CC
Supply Output for CMOS RAM. When V
V
V
Main Supply Input
Battery Status Output. High in normal operating mode when V
wise low. V
Reset Input. Connect to an external resistor divider to select the reset threshold. The
reset threshold can be programmed anywhere in the V
Power-Fail Comparator Input. When PFI is less than V
PFO goes low; otherwise, PFO remains high (see Power-Fail Comparator section).
Connect to V
Logic Output/External Bypass Switch-Driver Output. High when OUT switches to BATT.
Low when OUT switches to V
BATT ON for I
Ground
Power-Fail Comparator Output. When PFI is less than V
V
tery freshness seal (see B attery Freshness Seal , and Power-Fail Comparator sections).
Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as
MR is low and for 200ms after MR returns high. The active-low input has an internal
70µA pull-up current. In can be driven from a TTL- or CMOS-logic line or shorted to
ground with a switch. Leave open if unused.
Watchdog Output. WDO goes low if WDI remains either high or low for longer than the
watchdog timeout period. WDO returns high on the next transition of WDI. WDO is a
logic high for V
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout
period, the internal watchdog timer runs out and WDO goes low. WDO returns high on
the next transition of WDI. Connect WDO to MR to generate a reset due to a watchdog
fault.
Chip-Enable Input. The input to the chip-enable gating circuit. Connect to GND if unused
Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted.
If CE IN is low when reset is asserted, CE OUT will remain low for 10µs or until CE IN
goes high, whichever occurs first. CE OUT is pulled up to OUT.
Active-High Reset Output. Sources and sinks current. RESET is the inverse of RESET.
Early Power-Fail Warning Output. Low when V
generate an NMI to provide early warning of imminent power-failure.
Open-Drain, Active-Low Reset Output. Pulses low for 200ms when triggered, and stays
low whenever V
for 200ms after either V
(WDO connected to MR), or MR goes low to high.
Backup-Battery Input. When V
BATT. When V
V
used.
BATT
CC
SW
CC
. V
, PFO goes low; otherwise, PFO remains high. PFO is also used to enable the bat-
falls below V
, OUT is connected to V
BATT
BATT
may exceed V
CC
OUT
CC
SW
CC
is checked continuously. Disabled and logic low while V
if unused.
SW
rises above the reset threshold or above V
requirements exceeding 75mA.
< V
is below the reset threshold or when MR is a logic low. It remains low
and V
CC
CC
< V
CC
BATT
rises above the reset threshold, the watchdog triggers a reset
RST
CC
. Connect V
CC
CC
, BATT connects to OUT.
. Connect the base/gate of PNP/PMOS transistor to
, and low when V
Supervisory Circuits
through an internal P-channel MOSFET switch. When
falls below V
FUNCTION
CC
CC
rises above the reset threshold or above
, OUT, and BATT together if no battery is
CC
SW
falls to V
CC
and V
is below V
PFT
SW
PFT
BATT
or when V
LR
to 5.5V range.
or when V
. This output can be used to
BATT
BATT
, OUT switches from V
SW
, OUT reconnects to
exceeds V
.
CC
CC
CC
falls below V
falls below
is below V
BOK
, other-
CC
SW
SW
to
,
.
7