MAX793 Maxim, MAX793 Datasheet - Page 16

• Manufacturer Part Number: MAX793
• Description: 3.0V/3.3V Adjustable Microprocessor Supervisory Circuits
• Manufacturer: Maxim

Initial versions of the MAX793 and MAX794 have a
logic design error that can cause the loss of output volt-
age (OUT) when V
battery is connected to the BATT input. Applications
that do not use the MR input (including all MAX795
applications) are unaffected by this phenomenon.
Also, applications that do not use PFO are unaffected if
PFI is tied to V
The loss of output voltage is caused by the IC incor-
rectly entering the battery “freshness seal” mode.
Normally, freshness seal mode is activated by ground-
ing PFO during a power-up reset timeout period. Then,
the removal of V
necting the backup battery to OUT.
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
Figure 14. Driving an External Transistor with BATT ON
Figure 15. Using a SuperCap™ as a Backup Source
16
____________________________Erratum
(a)
______________________________________________________________________________________
3.0V OR 3.3V
(a)
3.0V OR 3.3V
1N4148
0.47F
CC
.
CC
V
CC
BATT
CC
powers the IC down without con-
is absent even though a backup
V
CC
MAX793
MAX794
MAX793
MAX794
MAX795
GND
BATT ON
GND
RESET
OUT
OUT
V
CC
TO STATIC
RAM
TO P
TO CMOS RAM
The IC decides whether or not to enter freshness seal
mode during all reset timeout periods. During a power-
up reset timeout period (which occurs when V
raised above the MAX793’s reset threshold or the volt-
age on the MAX794’s RESET IN pin is raised above the
RESET IN threshold), the IC momentarily disconnects
the PFO pin from the comparator output and lightly
pulls PFO up to V
is then tested and, if it is low, freshness seal mode is
chosen. (PFO is reconnected to the comparator output
before the end of the reset timeout period.)
However, when a reset is initiated by MR, the PFO pin
incorrectly remains connected to the comparator output
during the entire timeout period and is not pulled up. If
the comparator is driving PFO low during an MR reset
(b)
(b)
+5V
1N4148
3.0V OR
0.47F
3.3V
V
BATT
CC
CC
. The voltage level on the PFO pin
V
CC
MAX793
MAX794
MAX793
MAX794
MAX795
D
GND
BATT ON
G
GND
PMOS FET
S
BODY DIODE
RESET
OUT
OUT
V
CC
TO STATIC
RAM
TO P
CC
is