MAX7032 Maxim Integrated Products, MAX7032 Datasheet - Page 25

• Manufacturer Part Number: MAX7032
• Description: ASK/FSK Transceiver
• Manufacturer: Maxim Integrated Products

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The AGC dwell time is dependent on the crystal fre-
quency and the bit settings of the AGC dwell timer. To
calculate the dwell time, use the following equation:
where K is an odd integer in decimal from 9 to 23; see
Table 11.
To calculate the value of K, use the following equation
and use the next odd integer higher than the calculated
result:
For Manchester Code (50% duty cycle), set the dwell
time to at least twice the bit period. For NRZ data, set
the dwell to greater than the period of the longest string
of zeros or ones. For example, using Manchester Code
at 315MHz (f
4kbps (bit period = 125µs), the dwell time needs to be
greater than 250µs:
Choose the register value to be the next odd integer value
higher than 11.553, which is K = 13. The default value of
the AGC dwell timer on power-up or rest is zero (K = 9).
Table 11. AGC Dwell Timer Configuration
(Address 0x03)
Table 12. Off-Timer (t
DT2
K ≥ 3.3 x log
0
0
0
0
1
1
1
1
OFPS1
0
0
1
1
K ≥ 3.3 x log
ASK/FSK Transceiver with Fractional-N PLL
XTAL
DT1
0
0
1
1
0
0
1
1
Dwell Time
Low-Cost, Crystal-Based, Programmable,
10
______________________________________________________________________________________
= 12.679MHz) with a data rate of
(250µs x 12.679MHz) ≈ 11.553
10
DT0
(Dwell Time x f
0
1
0
1
0
1
0
1
OFF
=
OFPS0
f
0
1
0
1
XTAL
2
K
) Configuration
K = 9
K = 11
K = 13
K = 15
K = 17
K = 19
K = 21
K = 23
DESCRIPTION
XTAL
)
TIME BASE
1920µs
7680µs
120µs
480µs
t
OFF
The MAX7032 must be calibrated to ensure accurate
timing of the off timer in discontinuous receive mode or
when receiving FSK signals. The first step in calibration
is ensuring that the oscillator frequency register (regis-
ter: 0x05) has been programmed with the correct divi-
sor value (see the Oscillator Frequency Register
section). Next, enable the mixer to turn the crystal dri-
ver on.
Calibrate the polling timer by setting PCAL = 1 in the
control register (register 0x01, bit 3). Upon completion,
the PCALD bit in the status register (register 0x1A,
bit 1) is 1, and the PCAL bit is reset to zero. If using the
MAX7032 in continuous receive mode, polling timer
calibration is not needed.
To calibrate the FSK receiver, set FCAL = 1. Upon
completion, the FCALD bit in the status register (regis-
ter 0x08) is one, and the FCAL bit is reset to zero.
When in continuous receive mode and receiving FSK
data, recalibrate the FSK receiver after a significant
change in temperature or supply voltage. An autocal fea-
ture is provided that performs a calibration every minute
(ACAL bit, Table 8). When in discontinuous receive
mode, the polling timer and FSK receiver (if enabled) are
automatically calibrated every wake-up cycle.
The off timer, t
is configured using register 0x06 for the upper byte,
register 0x07 for the lower byte, and bits OFPS1 and
OFPS0 in the configuration 0 register (register 0x02, bit
3 and bit 2, respectively). Table 12 summarizes the
configuration of the t
bits set the size of the shortest time possible (t
base). The data written to the t
0x06 and register 0x07) are multiplied by the time base
to give the total t
power-up, the off-timer registers are reset to zero and
must be written before using DRX mode.
REG 0x06 = 0x00;
REG 0x07 = 0x01
OFF
MIN t
OFF
1.92ms
7.68ms
120µs
480µs
(see Figure 10), is a 16-bit timer that
OFF
OFF
time. See the example below. On
timer. The OFPS1 and OFPS0
OFF
REG 0x06 = 0xFF;
REG 0x07 = 0xFF
registers (register
Off Timer (t
MAX t
8 min 23s
2 min 6s
31.46s
7.86s
Calibration
OFF
OFF
OFF
time
25
)