MAX7032 Maxim Integrated Products, MAX7032 Datasheet - Page 24

• Manufacturer Part Number: MAX7032
• Description: ASK/FSK Transceiver
• Manufacturer: Maxim Integrated Products

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The MAX7032 has an internal frequency divider that
divides down the crystal frequency to 100kHz. The
MAX7032 uses the 100kHz clock signal when calibrat-
ing itself and also to set image-rejection frequency. The
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
Table 9. Status Register (Read Only) (Address: 0x1A)
Table 10. Clock Output Divider Ratio
Configuration
24
CKOUT
0
1
1
1
1
CLKON
PCALD
______________________________________________________________________________________
GAINS
FCALD
BIT ID
LCKD
Oscillator Frequency Register (Address 0x05)
X
X
X
CDIV1
X
0
0
1
1
Lock detect
AGC gain state
Clock/crystal alive
None
None
None
Polling timer calibration
done
FSK calibration done
CDIV0
BIT NAME
X
0
1
0
1
Disabled at logic 0
f
f
f
f
XTAL
XTAL
XTAL
XTAL
/ 2
/ 4
/ 8
FREQUENCY
CLOCKOUT
BIT LOCATION
(0 = LSB)
7
6
5
4
3
2
1
0
hexadecimal value written to the oscillator frequency
register is the nearest integer result of f
For example, if data is being received at 315MHz, the
crystal frequency is 12.67917MHz. Dividing the crystal
frequency by 100kHz and rounding to the nearest inte-
ger gives 127, or 0x7F hex. So for 315MHz, 0x7F would
be written to the oscillator frequency register.
The AGC dwell timer holds the AGC in low-gain state
for a set amount of time after the power level drops
below the AGC switching threshold. After that set
amount of time, if the power level is still below the AGC
threshold, the LNA goes into high-gain state. This is
important for ASK since the modulated data may have
a high level above the threshold and a low level below
the threshold, which without the dwell timer would
cause the AGC to switch on every bit.
1 = Internal PLL is locked
0 = Internal PLL is not locked so the
MAX7032 does not receive or transmit data
1 = LNA in high-gain state
0 = LNA in low-gain state
1 = Valid clock at crystal inputs
0 = No valid clock signal seen at the crystal
inputs
Zero
Zero
Zero
1 = Polling timer calibration is completed
0 = Polling timer calibration is in progress or
not completed
1 = FSK calibration is completed
0 = FSK calibration is in progress or not
completed
AGC Dwell Timer (Address 0x03)
FUNCTION
XTAL
/ 100kHz.