MAX7032 Maxim Integrated Products, MAX7032 Datasheet - Page 18

• Manufacturer Part Number: MAX7032
• Description: ASK/FSK Transceiver
• Manufacturer: Maxim Integrated Products

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The XTAL oscillator in the MAX7032 is designed to pre-
sent a capacitance of approximately 3pF between the
XTAL1 and XTAL2 pins. In most cases, this corre-
sponds to a 4.5pF load capacitance applied to the
external crystal when typical PC board parasitics are
added. It is very important to use a crystal with a
load capacitance that is equal to the capacitance of
the MAX7032 crystal oscillator plus PC board para-
sitics. If a crystal designed to oscillate with a different
load capacitance is used, the crystal is pulled away
from its stated operating frequency, introducing an
error in the reference frequency. Crystals designed to
operate with higher differential load capacitance
always pull the reference frequency higher.
In actuality, the oscillator pulls every crystal. The crys-
tal’s natural frequency is really below its specified fre-
quency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
Figure 7. Serial Interface Timing Diagram
18
f
P
=
______________________________________________________________________________________
SCLK
C
DIO
CS
2
m
t
SC
⎛
⎜
⎝
C
HI-Z
CASE
t
CSS
t
DS
+
1
C
LOAD
Crystal Oscillator (XTAL)
t
DH
−
C
CASE
t
DATA IN
CS
1
+
C
t
CL
SPEC
t
CH
⎞
⎟ ×
⎠
t
10
TH
6
where:
f
C
C
C
C
When the crystal is loaded as specified, i.e., C
C
The MAX7032 programs through a 3-wire interface. The
data input must follow the timing diagrams shown in
Figures 7, 8, and 9.
Note that the DIO line must be held LOW while CS is
high. This is to prevent the MAX7032 from entering dis-
continuous receive mode if the DRX bit is high. The
data is latched on the rising edge of SCLK, and there-
fore must be stable before that edge. The data
sequencing is MSB first, the command (C[1:0] see
Table 2), the register address (A[5:0] see Table 3), and
the data (D[7:0] see Table 4).
Table 2. Command Bits
p
m
CASE
SPEC
LOAD
SPEC
HI-Z
is the amount the crystal frequency is pulled in ppm.
is the motional capacitance of the crystal.
, the frequency pulling equals zero.
t
is the specified load capacitance.
is the case capacitance.
is the actual load capacitance.
DV
C[1:0]
0x0
0x1
0x2
0x3
D7
Serial Control Interface
Communication Protocol
DATA OUT
t
DO
DESCRIPTION
No operation
Master reset
Read data
Write data
D0
HI-Z
t
CSH
t
TR
LOAD
=