WM8731 Wolfson Microelectronics Ltd., WM8731 Datasheet - Page 35

• Manufacturer Part Number: WM8731
• Description: WM8731 : Low Power Audio Codec With Integrated Headphone Driver
• Manufacturer: Wolfson Microelectronics Ltd.

WM8731
Advanced Information
In all modes DACLRC and ADCLRC must always change on the falling edge of BCLK, refer to Figure
25, Figure 26, Figure 27 and Figure 28.
Operating the digital audio interface in DSP mode allows ease of use for supporting the various
sample rates and word lengths. The only requirement is that all data is transferred within the correct
number of BCLK cycles to suit the chosen word length.
In order for the digital audio interface to offer similar support in the three other modes (Left Justified,
2
I
S and Right Justified), the DACLRC, ADCLRC and BCLK frequencies, continuity and mark-space
ratios need more careful consideration.
In Slave mode, DACLRC and ADCLRC inputs are not required to have a 50:50 mark-space ratio.
BCLK input need not be continuous. It is however required that there are sufficient BCLK cycles for
each DACLRC/ADCLRC transition to clock the chosen data word length. The non-50:50 requirement
on the LRCs is of use in some situations such as with a USB 12MHZ clock. Here simply dividing
down a 12MHz clock within the DSP to generate LRCs and BCLK will not generate the appropriate
DACLRC or ADCLRC since they will no longer change on the falling edge of BCLK. For example,
with 12MHz/32k fs mode there are 375 MCLK per LRC. In these situations DACLRC/ADCLRC can
be made non 50:50.
In Master mode, DACLRC and ADCLRC will be output with a 50:50 mark-space ratio with BCLK
output at 64 x base frequency (i.e. 48 Khz).. The exception again is in USB mode where BCLK is
always 12MHz. So for example in 12MHz/32k fs mode there are 375 master clocks per DACLRC
period. Therefore DACLRC and ADCLRC outputs will have a mark space ratio of 187:188.
The ADC and DAC digital audio interface modes are software configurable as indicated in Table 13.
Note that dynamically changing the software format may result in erroneous operation of the
interfaces and is therefore not recommended.
The length of the digital audio data is programmable at 16/20/24 or 32 bits. Refer to the software
control table below. The data is signed 2’s complement. Both ADC and DAC are fixed at the same
data length. The ADC and DAC digital filters process data using 24 bits. If the ADC is programmed to
output 16 or 20 bit data then it strips the LSBs from the 24 bit data. If the ADC is programmed to
output 32 bits then it packs the LSBs with zeros. If the DAC is programmed to receive 16 or 20 bit
data, the WM8731 packs the LSBs with zeros. If the DAC is programmed to receive 32 bit data, then
it strips the LSBs.
The DAC outputs can be swapped under software control using LRP and LRSWAP as shown in
Table 14. Stereo samples are normally generated as a Left/Right sampled pair. LRSWAP reverses
the order so that a Left sample goes to the right DAC output and a Right sample goes to the left DAC
output. LRP swaps the phasing so that a Right/Left sampled pair is expected and preserves the
correct channel phase difference.
To accommodate system timing requirements the interpretation of BCLK maybe inverted, this is
controlled vias the software shown in Table 14. This is especially appropriate for DSP mode.
ADCDAT lines are always outputs. They power up and return from standby low.
DACDAT is always an input. It is expected to be set low by the audio interface controller when the
WM8731 is powered off or in standby.
ADCLRC, DACLRC and BCLK can be either outputs or inputs depending on whether the device is
configured as a master or slave. If the device is a master then the DACLRC and BCLK signals are
outputs that default low. If the device is a slave then the DACLRC and BCLK are inputs. It is
expected that these are set low by the audio interface controller when the WM8731 is powered off or
in standby.
AI Rev 2.3 August 2001
35