WM8141 Wolfson Microelectronics Ltd., WM8141 Datasheet - Page 29

• Manufacturer Part Number: WM8141
• Description: WM8141 : 12-BIT 6MSPS Cis/ccd Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

Production Data
WOLFSON MICROELECTRONICS LTD
COLOUR LINE-BY-LINE
Figure 26 Block Diagram Of Colour Line-By-Line Application, AC Coupled
Table 10 Typical Control Register Settings for Figure 26 (CDS, Negative-Going CCD
NAME
Set-up
register 1
Set-up
register 2
Set-up
register 3
Set-up
register 4
Set-up
register 5
Set-up
register 6
Maximum pixel rate = 1.5Mpixels/second (Mode 6)
Maximum pixel rate = 2Mpixels/second (Mode 2)
Maximum pixel rate = 4Mpixels/second (Mode 3)
Maximum pixel rate = 6Mpixels/second (Mode 4)
S
E
N
S
O
R
REGISTER
Video Signal, MCLK/VSMP = 2:1/3:1/6:1/8:1)
V
OUT
ADDRESS
000001
000010
000011
000101
001000
001001
datasheet for
See sensor
SENSOR TIMING
BUFFER
details
HEX
0B
23
20
1F
00
00
C
SETTING
0010 0X11
00XX 1111 LINEBYLINE = 1: Line by line mode selected;
0010 0000
0000 0000
0000 0000
BINARY
01 1111
RINP
RECOMMENDED
COMPONENTS
WM8141
INCLUDING
EXTERNAL
NOTE
EN = 1: Device enabled;
CDS = 1: CDS enabled;
MONO = X: Forced internally when LINEBYLINE
is set;
SELPD = 0: No selective power down;
PGAFS[1:0] = 10: ADC range optimised for
negative going video;
MODE4 = 0: set high if MCLK:VSMP ratio of 2:1
is required.
MUXOP[1:0] = 00: 12-bit parallel output;
INVOP = 0: Output data not inverted;
VRLCEXT = 0: RLCDAC required to provide
reset level clamp voltage since sensor is
AC coupled;
RLCDACRNG = 1: RLCDAC range is 0V to V
DEL[1:0] = 00: Default latency.
RLCV[3:0] = 1111: RLCDAC full scale voltage;
CDSREF[1:0] = 01: Default reset sample
position;
CHAN[1:0] = XX: Colour mode so not required.
ACYCNRLC = 1: Auto-cycling required;
FME = 1: Input mux controlled by FME bits;
RLCINT = 1: RLC performed on every pixel;
INTM[1:0] = XX: PGA/Offset multiplexers
controlled by auto-cycling so these bits have
no effect;
FME[1:0] = 00: Controls input multiplexer to
select red channel.
Only used if programmable VSMP circuit is
required.
Green and blue channels are automatically
powered down when LINEBYLINE = 1.
CONTROL I/F
CLOCKS
DATA
PD Rev 3.0 October 2000
SYSTEM
ASIC
WM8141
RT
;
29