WM8141 Wolfson Microelectronics Ltd., WM8141 Datasheet - Page 19

• Manufacturer Part Number: WM8141
• Description: WM8141 : 12-BIT 6MSPS Cis/ccd Analogue Front End/digitiser
• Manufacturer: Wolfson Microelectronics Ltd.

Production Data
LINE-BY-LINE OPERATION
WOLFSON MICROELECTRONICS LTD
Certain linear sensors (e.g Contact Image Sensors) give colour output on a line-by-line basis. i.e a
full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to
accommodate this type of signal the WM8141 can be set into Monochrome mode, with the input
channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8141
can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is
set the green and blue processing channels are powered down and the device is forced internally to
only operate in MONO mode (because only one colour is sampled at a time) through the red channel.
Figure 17 shows the signal path when operating in colour line-by-line mode.
Figure 17 Signal Path When in Line-by-Line Mode
In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be auto-
cycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit.
The multiplexers change on the first MCLK rising edge after RLC/ACYC is taken high. Alternatively,
all three multiplexers can be controlled via the serial interface by writing to register bits INTM[1:0] to
select the desired colour. It is also possible for the input multiplexer to be controlled separately from
the PGA and Offset multiplexers. Table 4 describes all the multiplexer selection modes that are
possible.
Table 4 Colour Selection Description in Line-by-Line Mode
GINP
FME
RINP
BINP
0
0
1
1
VRLC/VBIAS
ACYCNRLC
RLC
RLC
RLC
RLC
DAC
0
1
0
1
CL
4
INPUT
MUX
Internal,
no force mux
Auto-cycling,
no force mux
Internal,
force mux
Auto-cycling,
force mux
R
CDS
S
V
NAME
S
TIMING CONTROL
VSMP
R
G
B
R
G
B
OFFSET
MUX
PGA
MUX
MCLK
8
Input mux, offset and gain registers determined by
internal register bits INTM1, INTM0.
Input mux, offset and gain registers auto-cycled, RINP
Input mux selected from internal register bits FM1, FM0;
Offset and gain registers selected from internal register
bits INTM1, INTM0.
Input mux selected from internal register bits FM1, FM0;
Offset and gain registers auto-cycled, RINP
BINP
OFFSET
DAC
GINP
RINP… on RLC/ACYC pulse.
+
BINP
PGA
8
I/P SIGNAL
POLARITY
ADJUST
DESCRIPTION
RINP… on RLC/ACYC pulse.
+
12-BIT
CONFIGURABLE
ADC
INTERFACE
PARALLEL
CONTROL
PD Rev 3.0 October 2000
SERIAL/
WM8141
PORT
DATA
I/O
WM8141
GINP
OP[11:0]
SEN/STB
SCK/RNW
SDI/DNA
RLC/ACYC
19