MAX3675ECJ Maxim, MAX3675ECJ Datasheet - Page 8

• Manufacturer Part Number: MAX3675ECJ
• Description: 622Mbps / Low-Power / 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
• Manufacturer: Maxim

622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
The phase detector produces a voltage proportional to
the phase difference between the incoming data and
the internal clock. Because of its feedback nature, the
PLL drives the error voltage to zero, aligning the recov-
ered clock to the incoming data. The external phase
adjustment pins (PHADJ+, PHADJ-) allow the user to
vary the internal phase alignment.
A frequency detector incorporated into the PLL aids
frequency acquisition during start-up conditions. The
input data stream is sampled by quadrature compo-
nents of the VCO clock, generating a difference fre-
quency. Depending on the polarity of the difference
frequency, the PFD drives the VCO so that the differ-
ence frequency is reduced to zero. Once frequency
acquisition is obtained, the frequency detector returns
to a neutral state.
The VCO is fully integrated, while the loop filter requires
an external R-C network. This filter network determines
the bandwidth and peaking of the second-order PLL.
The RSSI output voltage is insensitive to temperature
and supply fluctuations. The power detector functions
as a broadband power meter that detects the total RMS
power of all signals within the detector bandwidth
(including input signal noise). The RSSI voltage varies
linearly (in decibels) for inputs of 2mVp-p to 50mVp-p.
The slope over this input range is approximately
29mV/dB.
The high-speed RSSI signal is filtered to an RMS level
with one external capacitor tied from CFILT to V
impedance looking into CFILT is about 500Ω to V
a result, the lower -3dB cutoff frequency is set by the
following simple relationship:
For 622Mbps applications, Maxim recommends a cut-
off frequency of 6.8kHz, which requires C
RSSI output is designed to drive a minimum load resis-
tance of 10k
Loads greater than 20pF must be buffered by a series
resistance of 10k (i.e., voltmeter).
The on-chip limiting amplifier provides more than 42dB
of gain. A low-frequency feedback loop is integrated
8
__________________Design Procedure
_______________________________________________________________________________________
f
to ground and a maximum of 20pF.
FILT
= 1 / 2 500
Received-Signal-Strength
Input Offset Correction
Loop Filter and VCO
Frequency Detector
Indicator (RSSI)
Phase Detector
C
F
F
= 47nF. The
CC
CC
. The
. As
into the MAX3675 to remove the input offset. DC cou-
pling to the ADI+ and ADI- inputs is not allowed, as this
would prevent the proper functioning of the DC offset-
correction circuitry.
The differential input impedance (Z
2.5k . The impedance between OLC+ and OLC- (Z
is approximately 120k . Take care when setting the
combined low-frequency cutoff (f
input DC-blocking capacitor (C
tion loop capacitor (C
the values of C
These values ensure that the poles associated with C
and C
lower -3dB corner frequency (no gain peaking).
C
or better in order to minimize f
must be a capacitor of type Z5U or better.
A LOP monitor with a user-programmable threshold
and a hysteresis comparator is also included with the
limiting amplifier circuitry. Internally, one comparator
input is tied to the RSSI output signal, and the other is
tied to the threshold voltage (V
nally and provides a trip point for the LOP indication. A
low-voltage, low-drift op amp, referenced to an internal
bandgap voltage (1.18V), is supplied for programming
a supply-independent threshold voltage. This op amp
requires two external resistors to program the LOP trip
point. V
the equation:
The op amp can source only 20µA of current.
Therefore, an R1 value greater than or equal to 100kΩ
is recommended for proper operation. The input bias
Table 1. Setting the Low-Frequency Cutoff
IN
must be a low-TC, high-quality capacitor of type X7R
0.022µF
0.010µF
6800pF
4700pF
2200pF
1000pF
OLC
470pF
330pF
220pF
C
TH
IN
work together to provide a flat response at the
is programmable from 1.18V to 2.4V using
V
IN
TH
and C
Loss-of-Power (LOP) Monitor
= 1.18 1 + R2 / R1
OLC
OLC
0.047µF
0.033µF
0.022µF
0.010µF
4700pF
3300pF
1000pF
680pF
470pF
). Refer to Table 1 for selecting
C
OLC
.
CUTOFF
IN
TH
) and the offset correc-
), which is set exter-
CUTOFF
IN
) is approximately
COMBINED LOW
deviations. C
f
CUTOFF
), due to the
13.5
135
190
290
3.0
6.8
10
29
68
(kHz)
OLC
OLC
IN
)