MAX3675ECJ Maxim, MAX3675ECJ Datasheet - Page 10

• Manufacturer Part Number: MAX3675ECJ
• Description: 622Mbps / Low-Power / 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
• Manufacturer: Maxim

622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
The MAX3675 is optimally designed to acquire lock and
to provide a bit-error rate (BER) of less than 10
strings of consecutive zeros and ones. Using the recom-
mended external component values of R
and C
MAX3675 can tolerate 1000 consecutive ones or zeros. It
is important to select a type of capacitor for C
temperature stability of ±10% or better. This ensures per-
formance over the -40°C to +85°C temperature range.
The MAX3675’s loss-of-lock (LOL) monitor indicates
when the PLL is locked. Under normal operation, the
loop is locked and the LOL output signal is high. When
the MAX3675 loses lock, a fast negative-edge transition
occurs on LOL. The output level remains at a low
level (held by C
(Figure 4).
Note that the LOL monitor is only valid when a data
stream is present on the inputs to the MAX3675. As a
result, LOL does not detect a loss-of-power condition
resulting from a loss of the incoming signal. See the
Loss-of-Power (LOP) Monitor section for this type of
indicator.
The MAX3675 digital data and clock I/Os (DDI+, DDI-,
SDO+, SDO-, SCLK+, and SCLK-) are designed to
interface with PECL signal levels. It is important to bias
these ports appropriately. A circuit that provides a
Thevenin equivalent of 50Ω to V
with fixed-impedance transmission lines for proper ter-
mination. Make sure that the differential outputs have
balanced loads.
Figure 4. Loss-of-Lock Output
10
______________________________________________________________________________________
F
= 2.2µF ±20%, measured results show that the
NO DATA
LOP
LOL
Input and Output Terminations
LOL
ACQUIRE
) until the loop reacquires lock
TIME
LOCKED
CC
- 2V should be used
Lock Detect
F
= 52.3Ω ±1%
F
-10
that has a
for long
The digital data input signals (DDI+ and DDI-) are dif-
ferential inputs to an emitter-coupled pair. As a result,
the MAX3675 can accept differential input signals as
low as 250mV. These inputs can also be driven single-
ended by externally biasing DDI- to the center of the
voltage swing.
The MAX3675’s performance can be greatly affected
by circuit board layout and design. Use good high-fre-
quency design techniques, including minimizing
ground inductance and using fixed-impedance trans-
mission lines on the data and clock signals. Power-sup-
ply decoupling should be placed as close to V
possible. Take care to isolate the input from the output
signals to reduce feedthrough.
There are three important requirements for driving the
limiting amplifier from a single-ended source (Figure 5):
1) There must be no DC coupling to the ADI+ and ADI-
2) The terminating resistor R
3) The low-frequency cutoff for the limiting amplifier
Figure 5. Single-Ended Input Termination
__________Applications Information
inputs. DC levels at these inputs disrupt the
offset-correction loop.
to the ADI- input to minimize common-mode coupling
problems.
is determined by either C
impedance or C
and R
T
0.22 F
= 50
C
b
the low-frequency cutoff is 29kHz.
Driving the Limiting Amplifier
R
50
b
C
0.22 F
T
b
/2 together with R
5.6nF
C
IN
T
(50 ) must be referenced
ADI+
IN
ADI-
and the 2.5k
T
. With C
MAX3675
Single-Ended
2.5k
b
= 0.22µF
CC
input
as