MAX3675 Maxim Integrated Products, MAX3675 Datasheet
MAX3675
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MAX3675 Summary of contents
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... Rev 4; 4/05 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier General Description The MAX3675 is a complete clock-recovery and data- retiming IC incorporating a limiting amplifier intend- ed for 622Mbps SDH/SONET applications and operates from a single +3.3V supply. The MAX3675 has two differential input amplifiers: one accepts PECL levels, while the other accepts small-sig- nal analog levels ...
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... TQFP (derate 13.1mW/°C above +85°C) .845.6mW + 0.5V) Operating Junction Temperature Range..............-40°C to +150° 0.5V) Storage Temperature Range ................................-65°C to +160°C CC Processing Temperature (die).............................................+400°C Lead Temperature (soldering,10s)......................................+300°C CONDITIONS MAX3675ECJ, INSEL = V PECL outputs INSEL = GND unterminated C = 0.01µF LOL ADI+, ADI- open (ADI+) - (ADI-) = 20mVp-p (ADI+) - (ADI-) = 80mVp-p 1MΩ ...
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... Serial Clock-to-Q Delay Serial Clock Frequency Note 3: AC parameters are guaranteed by design and characterization. Note 4: The MAX3675 is characterized with a PRBS of 2 Note 5: A lower minimum input voltage of 2mVp-p is achievable; however, the LOP hysteresis is not guaranteed below 3.6mVp-p. Note 6: Hysteresis = 20log(V RELEASE Note 7: Small-signal bandwidth cannot be measured directly ...
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Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier __________________________________________Typical Operating Characteristics (T = +25°C, unless otherwise noted.) A RECOVERED DATA AND CLOCK (SINGLE ENDED 520Ω PATTERN F DATA C = 0.022µ ...
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Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier ____________________________Typical Operating Characteristics (continued +25°C, unless otherwise noted.) A LOSS-OF-POWER HYSTERESIS vs. TEMPERATURE 4 PATTERN 3 +3.3V OR +5.0V CC 3.6 3.4 3.2 ...
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Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier PIN NAME 1 OLC+ Positive Offset-Correction Loop Capacitor Input 2 OLC- Negative Offset-Correction Loop Capacitor Input 3 RSSI Received-Signal-Strength Indicator Output 4, 8, 16, GND Supply Ground 24 ...
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... OLC- CFILT Figure 1. Functional Diagram Detailed Description Figure 1 shows the MAX3675’s architecture. It consists of a limiting amplifier input stage followed by a fully integrated clock/data-recovery (CDR) block implement- ed with a PLL. The input stage is selectable between a limiting amplifier or a simple PECL input buffer. The lim- iting amplifier provides an LOP monitor and an RSSI ...
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... Input Offset Correction The on-chip limiting amplifier provides more than 42dB of gain. A low-frequency feedback loop is integrated into the MAX3675 to remove the input offset. DC-cou- pling to the ADI+ and ADI- inputs is not allowed, as this 8 _______________________________________________________________________________________ would prevent the proper functioning of the DC offset- correction circuitry ...
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... R (Figure 2). The closed-loop bandwidth of a PLL is approximated by where K is the gain of the phase detector gain of the VCO, and Gm is the transconductance of the filter amplifier. For the MAX3675, an estimated value 7k MAX3675 F(S) GM FIL+ ...
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... The MAX3675’s LOL monitor indicates when the PLL is locked. Under normal operation, the loop is locked and the LOL output signal is high. When the MAX3675 loses lock, a fast negative-edge transition occurs on LOL. The output level remains at a low level (held by C the loop reacquires lock (Figure 4) ...
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... MAX3675 limiting amplifier, the power / receiver’s optical input power (x) increases factor of two, and the preamplifier is linear, then the voltage at the input to the MAX3675 also increases by a factor of two. The optical power increase is 10log( 10log(2) = +3dB. At the MAX3675, the voltage increase is: ( ...
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... As a result, the PDJ is dominated by the low- frequency cutoff of the preamplifier. When using a preamplifier without a highpass response with the MAX3675, the following equation provides a good starting point for choosing C Random Jitter (RJ) where t = duration of the longest run of consecutive L bits of the same value (seconds) ...
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... For a 1–0 bit stream, calculate PWD as follows: PWD = [(width of wider pulse) - (width of narrower pulse OLC (f ) The internal clock and data alignment in the MAX3675 well maintained close to the center of the data eye. Although not required, this sampling point can be shift- ed using the PHADJ inputs to optimize BER perfor- mance. The PHADJ inputs operate with differential input signals to approximately ± ...
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... Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier Pin Configuration TOP VIEW GND 25 DDI+ 26 DDI- 27 MAX3675 INSEL 28 ADI- 29 ADI CFILT 32 TQFP 14 ______________________________________________________________________________________ FIL+ GND FIL- 16 GND GND DDI SDO+ DDI- 13 SDO- INSEL ...
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Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) ______________________________________________________________________________________ Package Information PACKAGE OUTLINE, 32L TQFP, ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products Package Information (continued) PACKAGE OUTLINE, 32L TQFP, 5x5x1 ...