MAX194 Maxim, MAX194 Datasheet - Page 9

• Manufacturer Part Number: MAX194
• Description: 14-Bit / 85ksps ADC with 10A Shutdown
• Manufacturer: Maxim

If you read the data bits between conversions, you can
1) count CLK cycles until the end of the conversion, or
2) poll EOC to determine when the conversion is
3) generate an interrupt on EOC’s falling edge.
Note that the MSB conversion result appears at DOUT
after CS goes low but
subsequent SCLK pulse shifts out the next conversion
Figure 5. Gating CONV to Synchronize with CLK
Figure 6. Output Data Format, Reading Data During Conversion (Mode 1)
finished, or
(CASE 1)
(CASE 2)
CONV
DOUT
EOC
CLK
CLK
CS
CASE 1: CLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)
CASE 2: CLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)
NOTE: ARROWS ON CLK TRANSITIONS INDICATE LATCHING EDGE
14-Bit, 85ksps ADC with 10µA Shutdown
_______________________________________________________________________________________
START
CONV
CLK
before the first SCLK pulse. Each
B13 FROM PREVIOUS
START
CONVERSION
CONVERSION
t
DV
BEGINS
t
CW
B13
MSB
t
CD
t
CEH
B12
B11
B10
CONV
CLK
bit. The 15th SCLK pulse shifts out the sub-LSB (S0).
Additional clock pulses shift out zeros.
Data is clocked out on SCLK’s falling edge. Clock data
in on SCLK’s rising edge or, for clock speeds above
2.5MHz, on the following falling edge to meet the maxi-
mum SCLK-to-DOUT timing specification (Figure 7).
The maximum SCLK speed is 5MHz. See the Operating
Modes and SPI/QSPI Interfaces section for additional
information. When the conversion clock is near its maxi-
MAX194
LSB
B0
CONVERSION
S1
SUB-LSBs
ENDS
S0
SEE DIGITAL INTERFACE SECTION
t
CEL
B13
t
DH
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