MAX194 Maxim, MAX194 Datasheet - Page 10

• Manufacturer Part Number: MAX194
• Description: 14-Bit / 85ksps ADC with 10A Shutdown
• Manufacturer: Maxim

mum (1.7MHz), reading the data after each conversion
(during the acquisition time) results in lower throughput
(about 70ksps max) than reading the data during con-
versions, because it takes longer than the minimum
input acquisition time (four cycles at 1.7MHz) to clock
16 data bits at 5Mbps. After the data has been clocked
14-Bit, 85ksps ADC with 10µA Shutdown
Figure 8. MAX194 in the Simplest Operating Configuration
10
Figure 7. Output Data Format, Reading Data Between Conversions (Mode 2)
______________________________________________________________________________________
CASE 1: SCLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)
CASE 2: SCLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)
CASE 3: SCLK IDLES HIGH, DATA LATCHED ON FALLING EDGE (CPOL = 1, CPHA = 0)
(CASE 3)
(CASE 2)
(CASE 1)
DOUT
SCLK
SCLK
SCLK
EOC
CS
CONVERSION CLOCK
+5V
t
CONV
t
DV
10 F
t
CSS
MSB
B13
B12
0.1 F
t
SD
1
2
3
4
5
6
7
8
B11
BP/UP/SHDN
CLK
SCLK
VDDD
DOUT
DGND
EOC
CS
B10
MAX194
B9
in, leave some time (about 1µs) for any coupled noise
on AIN to settle before beginning the next conversion.
Whichever method is chosen for reading the data, con-
versions can be individually initiated by bringing CONV
low, or they can occur continuously by connecting EOC
to CONV. Figure 8 shows the MAX194 in its simplest
operational configuration.
NOTE: ARROWS ON SCLK TRANSITIONS INDICATE LATCHING EDGE
RESET
AGND
CONV
VDDA
VSSD
VSSA
B1
REF
AIN
16
15
14
13
12
11
10
9
LSB
B0
S1
SUB-LSBs
0.1 F
S0
ANALOG INPUT
REFERENCE (0V TO VDDA)
t
CSH
10 F
-5V
t
DH