MAX17036 Maxim Integrated Products, MAX17036 Datasheet - Page 21

• Manufacturer Part Number: MAX17036
• Description: (MAX17030 / MAX17036) 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
• Manufacturer: Maxim Integrated Products

w
w
When the main and other phase current-sense signals
(V
unbalanced, the transconductance amplifiers adjust the
other phase’s on-time, which increases or decreases
the phase inductor current until the current-sense sig-
nals are properly balanced:
where V
slave’s current-balance integrator, and Z
effective impedance at that node.
During phase overlap, t
phase 1’s on-time requirements, but reduced by 33%
when operating with three phases.
For a 3-phase regulator, each phase cannot be
enabled until the other 2 phases have completed their
on-time and the minimum off-times have expired. As
such, the minimum period is limited by 3 x (t
t
and maximum output voltage:
where:
so:
Hence, for a 7V input and 1.1V output, 500kHz is the
maximum switching frequency. Running at this limit is
not desirable as there is no room to allow the regulator
to make adjustments without triggering phase overlap.
For a 3-phase, high-current application with minimum
8V input, the practical switching frequency is 300kHz.
On-times translate only roughly to switching frequen-
cies. The on-times guaranteed in the Electrical
Characteristics are influenced by parasitics in the con-
duction paths and propagation delays. For loads above
the critical conduction point, where the dead-time effect
(LX flying high and conducting through the high-side
FET body diode) is no longer a factor, the actual
switching frequency (per phase) is:
where V
age drops in the inductor discharge and charge paths,
OFF(MIN)
t
ON SEC
CM
T
(
w
SW(MIN)
= V
)
t
T
DIS
ON(MAX)
=
=
= Main On-t t ime
CCI
). Maximum t
SW(MIN)
.
CMP
T
T
(
SW
SW
and V
f
= t
is the internal integrator node for each
SW
D
⎛
⎝ ⎜
⎛
⎝ ⎜
- V
V
V
OFF(MIN)
CCI
FB
CMN
= N
=
= V
CHG
______________________________________________________________________________________
+
a
V
+
V
t
0 07 7 5V
IN
ON
IN
0 075
PH
FB(MAX)
.
)
.
and V
+
ON
are the sum of the parasitic volt-
(
(
t
x (t
(
V
Secondary Current Balance Correctio
/[1/N
V
V
IN
is dependent on minimum V
⎞
⎠ ⎟
OUT
⎞
⎠ ⎟
ON
ON(MAX)
+
+
CS
a
T
/V
PH
SW
V
is calculated based on
IN(MIN
+
DIS
= V
⎛
⎝ ⎜
– V
V
S
I
DIS
CCI CCI
−
CSP
IN(MAX)
V
+ t
V
Z
IN
)
x T
CHG
h
OFF(MIN)
- V
SW(MIN)
⎞
⎠ ⎟
CSM
)
/V
e
IN(MIN)
CCI
) become
)
e
is the
ON
]
t
n n
IN
+
)
IMVP-6.5 VID Controllers
4
1/2/3-Phase Quick-PWM
including MOSFET, inductor, and PCB resistances;
V
inductor charge path, including high-side switch,
inductor, and PCB resistances; and t
as determined above.
The MAX17030/MAX17036 sense the output current of
each phase allowing the use of current-sense resistors
on inductor DCR as the current-sense element. Low-
offset amplifiers are used for current balance, voltage-
positioning gain, and current limit.
Using the DC resistance (R
allows higher efficiency. The initial tolerance and tem-
perature coefficient of the inductor’s DCR must be
accounted for in the output-voltage droop-error budget
and current monitor. This current-sense method uses
an RC filtering network to extract the current information
from the output inductor (see Figure 4). The RC network
should match the inductor’s time constant (L/R
and:
where R
and R
the typical inductance and R
the inductor manufacturer. To minimize the current-
sense error due to the current-sense inputs’ bias current
(I
and use the above equation to determine the sense
capacitance (C
ance and resistors with 1% tolerance specifications.
Temperature compensation is recommended for this
current-sense method. See the Voltage Positioning and
Loop Compensation section for detailed information.
When using a current-sense resistor for accurate out-
put-voltage positioning, the circuit requires a differential
RC filter to eliminate the AC voltage step caused by the
equivalent series inductance (L
sense resistor (see Figure 4). The ESL induced voltage
step might affect the average current-sense voltage.
The RC filter’s time constant should match the L
R
resistor’s parasitic inductance:
U
CHG
CSP_
SENSE
DCR
.
is the sum of the parasitic voltage drops in the
and I
CS
time constant formed by the current-sense
c
is the inductor’s series DC resistance. Use
is the required current-sense resistance,
CSN_
o
EQ
R
R
), choose R1//R2 to be less than 2kΩ
CS
R
CS
). Choose capacitors with 5% toler-
L
SENSE
m
ESL
=
=
⎛
⎝ ⎜
C
R
L
EQ
1
R
=
+
DCR
2
C
⎡
⎣ ⎢
R
R
EQ EQ
2
1
DCR
1
⎞
⎠ ⎟
) of the output inductor
+
R
R
R
ESL
DCR
1
values provided by
2
Current Sense
⎤
⎥
⎦
ON
) of the current-
is the on-time
DCR
):
ESL
21
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