MAX17036 Maxim Integrated Products, MAX17036 Datasheet - Page 14

• Manufacturer Part Number: MAX17036
• Description: (MAX17030 / MAX17036) 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
• Manufacturer: Maxim Integrated Products

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1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
14
______________________________________________________________________________________
PIN
15
16
17
18
19
PWRGD
NAME
TON
This low-voltage logic input indicates power usage and sets the operating mode together
with DPRSLPVR as shown in the truth table below. While DPRSLPVR is low, if
controller is immediately set to (N-1)-phase forced-PWM mode. The controller returns to N-phase
forced-PWM mode when
The controller is in N-phase skip mode during startup including boot mode, but is in N-phase
forced-PWM mode during the transition from boot mode to VID mode, during soft-shutdown,
irrespective of the DPRSLPVR and
connecting CSP2, CSP3 to VCC, then only phase 1 is active in the above modes.
Switching Frequency Setting Input. An external resistor between the input power source and this
pin sets the switching frequency according to the following equation:
where C
The external resistor must also satisfy the requirement [V
the minimum V
TON is high impedance in shutdown.
Clock Enable CMOS Push-Pull Logic Output Powered by V
when the output voltage sensed at FB is in regulation.
soft-start and soft-stop transitions.
additional 20µs after the transition is completed.
PWRGD startup delay period after
the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-
related PWRGD blanking period is complete and the output reaches regulation.
Open-Drain Power-Good Output. After output-voltage transitions, except during power-up and power-
down, if FB is in regulation, then PWRGD is high impedance.
PWRGD is low during startup, continues to be low while the output is at the boot voltage, and stays
low until 5ms (typ) after
high if FB is within the PWRGD threshold window.
PWRGD is forced low during soft-shutdown and while in shutdown. PWRGD is forced high
impedance whenever the slew-rate controller is active (output-voltage transitions), and continues
to be forced high impedance for an additional 20µs after the transition is completed.
The PWRGD upper threshold is blanked during any downward output-voltage transition that
happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled
internal-transition-related PWRGD blanking period is complete and the output reaches regulation.
A pullup resistor on PWRGD causes additional finite shutdown current.
Driver Skip Control Output. Push/pull logic output that controls the operating mode of the skip-
mode driver IC.
forced-PWM mode. When
operate in pulse-skipping mode.
instructing the external drivers to shut down.
DPRSLPVR
1
0
0
upper threshold is blanked during any downward output-voltage transition that happens when
TON
= 16.26pF.
IN
value expected in the application.
PSI
X
0
1
swings from V
Very low current (1-phase skip)
Intermediate power potential (N-1-phase PWM)
Max power potential (full-phase PWM: N-phase or 1 phase as set by user
at CSP2, CSP3)
is forced high.
goes low, after which it starts monitoring the FB voltage and goes
f
is low, the driver ICs enable their zero-crossing comparators and
SW
= 1/(C
DD
logic levels. However, if phases 2 and 3 are disabled by
is pulled low. See the startup timing diagram (Figure 9). The
goes low at the end of the soft-shutdown sequence,
to GND. When
is forced low during dynamic VID transitions and for an
TON
FUNCTION
x (R
Pin Description (continued)
TON
is the inverse of PWRGD, except for the 5ms
3P3
+ 6.5k ))
IN(MIN)
. This inverted logic output indicates
MODE
is forced high in shutdown and during
is high, the driver ICs operate in
/R
TON
]
10µA where V
is forced low, the
IN(MIN)
is