MAX15023 Maxim Integrated Products, MAX15023 Datasheet - Page 20

• Manufacturer Part Number: MAX15023
• Description: Dual-Output Synchronous Buck Controller
• Manufacturer: Maxim Integrated Products

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Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
It is recommended to have a phase margin around
+50° to +60° to maintain a robust loop stability and
well-behaved transient response.
If an electrolytic or large-ESR tantalum output capacitor
is used, the capacitor ESR zero f
between the LC poles and the crossover frequency f
(f
portional-integral) compensation network.
If a ceramic or low-ESR tantalum output capacitor is
used, the capacitor ESR zero typically occurs above
the desired crossover frequency f
f
tional-integral-derivative) compensation network.
If f
of the capacitor ESR zero almost cancels the phase
loss of one of the complex poles of the LC filter around
the crossover frequency. Therefore, a Type II compen-
sation network with a midband zero and a high-fre-
quency pole can be used to stabilize the loop. In Figure
4, R
C
high-frequency pole (f
the output high-frequency ripple.
To calculate the component values for Type II compen-
sation network in Figure 4, follow the instruction below:
1) Calculate the gain of the modulator (Gain
where V
amplitude of the ramp in the pulse-width modulator,
V
see Electrical Characteristics table), and V
desired output voltage.
The gain of the error amplifier (Gain
quencies is:
where g
20
ZO
PO
FB
CF
ZO
. In this situation, choose a Type III (PID or propor-
composed of the regulator’s pulse-width modulator,
LC filter, feedback divider, and associated circuitry
at crossover frequency:
F
in the Type II compensation network also provide a
Gain
is the FB_ input voltage set-point (0.6V typically,
< f
______________________________________________________________________________________
is lower than f
and C
ZO
m
IN
MOD
is the transconductance of the error amplifier.
< f
is the regulator’s input voltage, V
F
O
introduce a midband zero (f
). In this case, use a Type II (PI or pro-
Type II Compensation Network
=
V
V
OSC
Gain
IN
O
P1
and close to f
EA
×
), which mitigates the effects of
(
2π
=
g
×
m
f
ESR
O
×
R
×
O
F
L
ZO
, that is f
EA
PO
OUT
(See Figure 4)
) in midband fre-
typically occurs
, the phase lead
)
×
Z1
V
OUT
V
OSC
OUT
PO
). R
FB
MOD
< f
F
is the
is the
O
and
)—
O
<
The total loop gain as the product of the modulator gain
and the error amplifier gain at f
Therefore:
Solving for R
2) Set a midband zero (f
Solving for C
3) Place a high-frequency pole at f
Figure 4. Type II Compensation Network.
one of the LC poles):
attenuate the ripple at the switching frequency, f
and calculate C
V
V
OUT
V
OSC
IN
R
R
R
1
2
F
×
F
=
F
f
:
Z
(
:
2
V
1
C
C
π
V
OSC
Gain
=
REF
CF
F
×
2
=
f
CF
ESR
O
π
V
=
MOD
×
2
FB
×
×
π
using the following equation:
(
π
2π
R
L
×
×
1
×
F
OUT
R
R
×
V
×
×
Z1
F
F
IN
g
Gain
f
C
M
O
×
×
)
) at 0.75 x f
×
F
1
×
×
1
f
f
O
PO
SW
g
L
=
EA
V
m
should equal 1. So:
V
OUT
OUT
0 75
C
×
FB
R
−
×
.
F
F
= 1
0 75
C
ESR
.
P1
1
)
F
×
×
×
f
g
V
PO
= 0.5 x f
m
OUT
PO
×
R
(to cancel
F
COMP
C
=
CF
SW
1
SW
(to
)