MAX15023 Maxim Integrated Products, MAX15023 Datasheet - Page 10

• Manufacturer Part Number: MAX15023
• Description: Dual-Output Synchronous Buck Controller
• Manufacturer: Maxim Integrated Products

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Wide 4.5V to 28V Input, Dual-Output
Synchronous Buck Controller
10
PIN
13
14
15
16
17
18
19
20
21
22
23
24
—
______________________________________________________________________________________
PGOOD2
PGND2
COMP2
COMP1
NAME
SGND
LIM2
LIM1
V
DL2
FB2
RT
EP
IN
CC
Low-Side Gate-Driver Supply Return (Regulator 2). Connect to the source of the low-side MOSFET of
Regulator 2.
Low-Side Gate-Driver Output for Regulator 2. DL2 swings from V
reaches the UVLO rising threshold voltage.
Power-Good Output (Open Drain) for Channel 2. To obtain a logic signal, pull up PGOOD2 with an external
resistor connected to a positive voltage below 28V.
Internal 5.2V Linear Regulator Output and the Device’s Core Supply. When using the internal regulator,
bypass V
operation, then a 2.2μF ceramic capacitor is adequate for decoupling (see the Typical Application Circuits).
Feedback Input for Regulator 2. Connect FB2 to a resistive divider between output 2 and SGND to adjust
the output voltage between 0.6V and (0.85 x input voltage (V)). See the Setting the Output Voltage section.
Compensation Pin for Regulator 2. See the Compensation section.
Oscillator-Timing Resistor Input. Connect a resistor from RT to SGND to set the oscillator frequency from
200kHz to 1MHz (see Setting the Switching Frequency section.).
Signal Ground. Connect SGND to the SGND plane. SGND also serves as sensing input of the synchronous
MOSFET’s V
Internal V
linear regulator (V
Current-Limit Adjustment for Regulator 2. Connect a resistor (R
current-limit threshold (V
Cycle-by-Cycle Low-Side Source Peak Current Limit section.
Current-Limit Adjustment for Regulator 1. Connect a resistor (R
current-limit threshold (V
Cycle-by-Cycle Low-Side Source Peak Current Limit section.
Compensation Pin for Regulator 1. See the Compensation section.
Exposed Paddle. Connect EP to a large copper plane at SGND potential to improve thermal dissipation. Do
not use as the main IC’s SGND ground connection.
CC
CC
DS
to SGND with a 4.7μF minimum low-ESR ceramic capacitor. If V
Regulator Input. Bypass IN to SGND with a 1μF minimum ceramic capacitor when the internal
drop (source terminals) for both channels.
CC
) is used. When operating in the 5V ±10% range, connect IN to V
ITH2
ITH1
) from 30mV (R
) from 30mV (R
LIM2
LIM1
) = 6kΩ) to 300mV (R
FUNCTION
= 6kΩ) to 300mV (R
Pin Description (continued)
LIM2
LIM1
CC
) from LIM2 to SGND to adjust the
) from LIM1 to SGND to adjust the
to PGND2. DL2 is low before V
LIM2
LIM1
= 60kΩ). See the Setting the
= 60kΩ). See the Setting the
CC
is connected to IN for 5V
CC
.
CC