XR16L580 Exar Corporation, XR16L580 Datasheet - Page 22

• Manufacturer Part Number: XR16L580
• Description: Smallest 2.25 to 5.5V Uart With 16-Byte Fifo And Power-save
• Manufacturer: Exar Corporation

XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
See “RECEIVER” on page 12.
See “Transmitter” on page 11.
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter. The rate is
programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’.
“Programmable Baud Rate Generator” on page 9.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
When FCR bit-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L580 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
4.4
4.4.1
4.4.2
A
A2-A0
DDRESS
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
T
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Baud Rate Generator Divisors (DLL and DLM) - Read/Write
Interrupt Enable Register (IER) - Read/Write
ABLE
IER versus Receive FIFO Interrupt Mode Operation
IER versus Receive/Transmit FIFO Polled Mode Operation
XOFF1
XOFF2
XON1
XON2
N
EFR
R
AME
EG
6: INTERNAL REGISTERS DESCRIPTION.
RD/WR
R
W
WR
WR
WR
WR
EAD
RITE
/
Enable
B
Auto
Bit-7
Bit-7
Bit-7
Bit-7
CTS
IT
-7
Enable
B
Auto
Bit-6
Bit-6
Bit-6
Bit-6
RTS
IT
-6
Enhanced Registers
Special
Select
B
Char
Bit-5
Bit-5
Bit-5
Bit-5
IT
-5
for more details.
22
MCR[7:5],
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[2]
Enable
B
Bit-4
Bit-4
Bit-4
Bit-4
IT
-4
S
HADED BITS ARE ENABLED WHEN
B
Soft-
ware
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
IT
-3
B
Soft-
ware
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
IT
-2
B
Soft-
ware
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Cntl
IT
-1
EFR B
B
Soft-
ware
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Cntl
áç
áç
áç
áç
IT
-0
IT
-4=1
LCR=0
C
REV. 1.2.0
OMMENT
X
See
BF