AD9430-170 Analog Devices, AD9430-170 Datasheet - Page 9

• Manufacturer Part Number: AD9430-170
• Description: 12-Bit, 170/210 MSPS 3.3 V A/D Converter
• Manufacturer: Analog Devices

REV. PrG 4/01/2002
PIN FUNCTION DESCRIPTIONS (LVDS mode )
LVDS Mode
Pin Number
2,42,43,44,45,46
1
3
5
6
7
8,14,15,18,19,24,27,28,29,34,
39,40,88,89,90,94,95,98,99
4,9,12,13,16,17,20,23,25,26,3
0,31,35,38,41,86,87,91,92,93,
96,97,100
10
11
21
22
32
33
36
37
47,54,62,75,83
48,53,61,67,74,82
49
50
51
52
55
56
57
58
59
60
63
64
65
66
68
69
70
71
72
73
76
77
78
79
80
81
84
85
PRELIMINARY TECHNICAL DATA
Name
DNC
S5
S4
S2
S1
LVDSBIAS
AV
AGND
SENSE
VREF
VIN+
VIN-
DS+
DS-
ENC+
ENC-
DrV
DrGND
D0_C
D0_T
D1_C
D1_T
D2_C
D2_T
D3_C
D3_T
D4_C
D4_T
DCO-
DCO+
D5_C
D5_T
D6_C
D6_T
D7_C
D7_T
D8_C
D8_T
D9_C
D9_T
D10_C
D10_T
D11_C
D11_T
OR_C
OR_T
DD
DD
Function in LVDS Mode
Do not connect
Full Scale Adjust pin : ‘1’ sets FS =
Interlaced or parallel output mode. (only in Dual Port mode
operation) HIGH = data arrives in channel A at falling edge of clock
and data arrives in channel A at rising edge of clock. LOW = data
arrives in channels A and B at rising edge of clock.
Output Mode select. Low = Dual Port, CMOS; High = LVDS
Data format select. Low = Binary, High = Two’s compliment
Sets LVDS Output Current = 3.5mA
(Place 3.7K RSET resistor from LVDSBIAS to ground)
3.3V analog supply. (3.0V to 3.6V)
Analog Ground
Control Pin for Reference , Full Scale
1.235 Reference I/O - function dependent on REFSENSE
Analog input – true.
Analog input – compliment.
Data sync (input) – Not used in LVDS mode.Tie LOW .
Data sync (input) – compliment. Not used in LVDS mode.Tie HIGH.
Clock input – true.
Clock input – compliment.
3.3V digital output supply.
Digital ground.
D0 complement output bit (LSB)
D0 true output bit (LSB)
D1 complement output bit
D1 true output bit
D2 complement output bit
D2 true output bit
D3 complement output bit
D3 true output bit
D4 complement output bit
D4 true output bit
Data Clock output – compliment. (LVDS Levels)
Data Clock output – true.
D5 complement output bit
D5 true output bit
D6 complement output bit
D6 true output bit
D7 complement output bit
D7 true output bit
D8 complement output bit
D8 true output bit
D9 complement output bit
D9 true output bit
D10 complement output bit
D10 true output bit
D11 complement output bit
D11 true output bit
Overrange complement output bit (LVDS Levels)
Overrange true output bit (LVDS Levels)
‘0’ sets FS = 1.533 V
-9-
(LVDS Levels)
(LVDS Levels)
(LVDS Levels)
(LVDS Levels)
(LVDS Levels)
(LVDS Levels)
(LVDS Levels)
(LVDS Levels)
(LVDS Levels)
(LVDS Levels) MSB
(LVDS Levels)
pp differential
(LVPECL levels)
(LVDS Levels)
(LVDS Levels)
(LVDS Levels)
(LVDS Levels)
(LVPECL levels)
(LVDS Levels)
(LVDS Levels)
(LVDS Levels)
(LVDS Levels)
(LVDS Levels)
(LVDS Levels) MSB
(LVDS Levels)
(LVDS Levels)
(LVDS Levels)
.766 V
(LVDS Levels)
pp differential,
AD9430