AD9430/PCB-CMOS Analog Devices, AD9430/PCB-CMOS Datasheet

AD9430/PCB-CMOS

Manufacturer Part Number

AD9430/PCB-CMOS

Description

12-Bit/ 170 MSPS 3.3V A/D Converter

Manufacturer

Analog Devices

Datasheet

1.AD9430PCB-CMOS.pdf (20 pages)

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REV. PrG 4/01/2002

Information furnished by Analog Devices is believed to be accurate and

reliable.However,no responsibility is assumed by Analog Devices for its use,nor

for any infringements of patents or other rights of third parties that may result from

its use.No license is granted by implication or otherwise under any patent or

patent rights of Analog Devices.

Preliminary Technical Data

FEATURES

SNR = 65dB @ Fin up to 65MHz at 170Msps

ENOB of 10.3 @ Fin up to 65MHz at 170 Msps

SFDR = -80dBc @ Fin up to 65MHz at 170Msps

Two Output Data options

700 MHz Full Power Analog Bandwidth

On–chip reference and track/hol d

1.5V Input voltage range

+3.3V Supply Operation

Data Sync input and Data Clock output provided

APPLICATIONS

Wireless and Wired Broadband Communications

Communications Test Equipment

Radar and Satellite sub-systems

Power Amplifier Linearization

Excellent Linearity:

Power dissipation = 1.25W typical at 170Msps

Output data format option

Interleaved or parallel data output option (CMOS)

Clock Duty Cycle Stabilizer.

- Demultiplexed 3.3V CMOS outputs each at 85 Msps

- LVDS at 170Msps

- Wideband carrier frequency systems

- DNL = +/- 1 lsb (typ)

- INL = +/- 1.5 lsb (typ)

Cable Reverse Path

ENC+

ENC-

DS+

DS-

AIN+

AIN-

PRELIMINARY TECHNICAL DATA

AD9430

Management

AD9430 FUNCTIONAL BLOCK DIAGRAM

Clock

Track &

Hold

(-1dBFs)

SENSE

Reference

Scaleable

VREF

Pipeline

12-bit

ADC

Core

PRODUCT DESCRIPTION

The AD9430 is a 12-bit monolithic sampling analog–to–

digital converter with an on–chip track–and–hold circuit and

is optimized for low cost, low power, small size and ease of

use. The product operates up to 170 Msps conversion rate

and is optimized for outstanding dynamic performance in

wideband carrier systems.

The ADC requires a +3.3V power supply and a differential

encode clock for full performance operation. No external

reference or driver components are required for many

applications. The digital outputs are TTL/CMOS or LVDS

compatible. Separate output power supply pins support

interfacing with 3.3V CMOS logic.

An output data format select option of two’s complement or

offset binary is supported. In CMOS mode two output buses

support demultiplexed data up to 85 Msps rates. A data sync

input is supported for proper output data port alignment and

a data clock output is available for proper output data timing.

Fabricated on an advanced BiCMOS process, the AD9430 is

available in a 100 pin surface mount plastic package (100

TQFP ePAD) specified over the industrial temperature range

(–40°C to +85°C).

AGND

Select CMOS or LVDS

One Technology Way,P.O.Box 9106,Norwood,MA 02062-9106,U.S.A.

Tel:781/329-4700

Fax:781/326-8703

DrGND

Outputs

CMOS

LVDS

DrV

3.3V A/D Converter

12-Bit, 170 MSPS

B port

A port

DCO+

Data(24), OR(2)

Data(12), OR(1)

DCO-

AD9430

www.analog.com

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AD9430/PCB-CMOS Summary of contents

Page 1

... ENC+ ENC- REV. PrG 4/01/2002 Information furnished by Analog Devices is believed to be accurate and reliable.However,no responsibility is assumed by Analog Devices for its use,nor for any infringements of patents or other rights of third parties that may result from its use.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...

Page 2

PRELIMINARY TECHNICAL DATA AD9430 (AV DC SPECIFICATIONS DD reference, LVDS Output Mode) Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error POWER SUPPLY REJECTION REFERENCE OUT (V ...

Page 3

PRELIMINARY TECHNICAL DATA 1 (AV AC SPECIFICATIONS = +85 C, Internal voltage reference, LVDS Output Mode ) Parameter (Conditions) SNR Analog Input 10 MHz @ -0.5dBFS 65 MHz 100 MHz 240 MHz SINAD Analog Input 10 MHz @ -0.5dBFS 65 ...

Page 4

PRELIMINARY TECHNICAL DATA AD9430 SWITCHING SPECIFICATIONS (cont’d) Parameter OUTPUT Parameters in Demux Mode Valid Time ( Propagation Delay ( Rise Time (t ) (20% to 80%) R Fall Time (t ) (20% to 80%) F DCO ...

Page 5

PRELIMINARY TECHNICAL DATA AD9430 Timing Diagram REV. PrG 4/01/2002 -5- AD9430 ...

Page 6

... Although the AD9430 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality Model AD9430BSV-170 AD9430/PCB-CMOS S1 S2 (Data (LVDS/CMOS Format ...

Page 7

PRELIMINARY TECHNICAL DATA DNC AGND LVDSBIAS 8 AVDD 9 AGND 10 SENSE 11 VREF 12 AGND 13 AGND 14 AVDD 15 AVDD 16 AGND AGND 17 18 AVDD 19 ...

Page 8

PRELIMINARY TECHNICAL DATA AD9430 PIN FUNCTION DESCRIPTIONS (CMOS mode) CMOS Mode Name Pin Number 2,7,42,43,65,66,68 DNC 8,14,15,18,19,24,27,28,29,34 39,40,88,89,90,94,95,98,99 4,9,12,13,16,17,20,23,25,26,3 AGND 0,31,35,38,41,86,87,91,92,93, 96,97,100 10 SENSE 11 VREF 21 VIN+ 22 VIN- ...

Page 9

PRELIMINARY TECHNICAL DATA PIN FUNCTION DESCRIPTIONS (LVDS mode ) LVDS Mode Name Pin Number 2,42,43,44,45,46 DNC LVDSBIAS 8,14,15,18,19,24,27,28,29,34 39,40,88,89,90,94,95,98,99 4,9,12,13,16,17,20,23,25,26,3 AGND 0,31,35,38,41,86,87,91,92,93, 96,97,100 10 SENSE 11 VREF 21 VIN+ ...

Page 10

PRELIMINARY TECHNICAL DATA AD9430 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of ...

Page 11

PRELIMINARY TECHNICAL DATA Signal -to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and ...

Page 12

PRELIMINARY TECHNICAL DATA AD9430 APPLICATION NOTES THEORY OF OPERATION The AD9430 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the ...

Page 13

PRELIMINARY TECHNICAL DATA Digital Outputs The off chip drivers on the chip can be configured by the user to provide CMOS or LVDS compatible output levels via pin S2. The CMOS digital outputs (S2=0) are TTL/CMOS- compatible for lower power ...

Page 14

PRELIMINARY TECHNICAL DATA AD9430 AD9430 EVALUATION BOARD The AD9430 evaluation board offers an easy way to test the AD9430. It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on ...

Page 15

PRELIMINARY TECHNICAL DATA DAC Outputs Each channel is reconstructed by an on-board dual-channel DAC, an AD9753. This DAC is intended to assist in debug—it should not be used to measure the performance of the ADC current output ...

Page 16

PRELIMINARY TECHNICAL DATA AD9430 No. Qty. Reference Designator 1 45 C1, C3–C11, C15–C17, C19–C29, C31–C48, C58–C62 C12, C13 4 1 C14 5 0 C18 6 7 C30, C49, C63–C67 7 9 E3–E1–E2 E19–E17–E18 E13–E11–E12 E26–E25–E27–E24 ...

Page 17

PRELIMINARY TECHNICAL DATA PTMICA04 PTMICA04 PTMICA04 P22 P4 P21 REV. PrG 4/01/2002 GND 82 DRVDD GND 86 GND 87 VCC 88 VCC 89 VCC 90 GND 91 GND 92 GND 93 ...

Page 18

PRELIMINARY TECHNICAL DATA AD9430 C64 C16 C17 C19 0 0.1 F 0.1 F GND VDL + C67 10 F GND DRV DD + C61 C62 C60 C65 C59 10 F 0.1 F 0.1 F ...

Page 19

PRELIMINARY TECHNICAL DATA REV. PrG 4/01/2002 -19- AD9430 ...

Page 20

... SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. The AD9430 Evaluation Board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose. ...

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