AD9430-170 Analog Devices, AD9430-170 Datasheet - Page 14

• Manufacturer Part Number: AD9430-170
• Description: 12-Bit, 170/210 MSPS 3.3 V A/D Converter
• Manufacturer: Analog Devices

AD9430
AD9430 EVALUATION BOARD
The AD9430 evaluation board offers an easy way to test the
AD9430. It requires a clock source, an analog input signal, and
a 3.3 V power supply. The clock source is buffered on the board
to provide the clocks for the ADC, an on-board DAC, latches,
and a data ready signal. The digital outputs and output clocks
are available at two 40-pin connectors, P3 and P4. The board
has several different modes of operation, and is shipped in the
following configuration:
• Offset Binary
• Internal Voltage Reference
• CMOS Parallel Timing
• Full-Scale Adjust = Low
Power Connector
Power is supplied to the board via a detachable 12-lead power
strip (three 4-pin blocks).
AVDD 3.3 V
DRVDD 3.3 V
VDL 3.3 V
EXT_VREF
VCLK/V_XTAL
VAMP
Analog Inputs
The evaluation board accepts a 1.3 V p-p analog input signal
centered at ground at SMB connector J4. This signal is terminated
to ground through 50 Ω by R16. The input can be alternatively
terminated at T1 transformer secondary by R13, R14. T1 is a
wideband RF transformer providing the single-ended to differential
conversion allowing the ADC to be driven differentially, minimizing
even order harmonics. An optional second transformer T2 can be
placed following T1 if desired. This would provide some perfor-
mance advantage (~1–2 dB) for high analog input frequencies
(>100 MHz). If T2 is placed, two shorting traces at the pads would
need to be cut. The analog signal is low pass filtered by R41,
C12, and R42, C13 at the ADC input.
Gain
Full scale is set at E17–E19, E17–E18 sets S5 low, full scale =
1.5 V differential; E17–E19 sets S5 high, full scale = 0.75 V
differential.
Encode
The encode clock is terminated to ground through 50 Ω at SMB
connector J5. The input is ac-coupled to a high-speed differential
receiver (LVEL16) which provides the required low-jitter, fast
edge rates needed for optimum performance. J5 input should be
LVEL16 clock buffer can be powered from AVDD or VCLK at E47 jumper
(AVDD, DrVDD,VDL are the minimum required power connections).
Table II. Power Connector
Analog Supply for ADC (~ 350 mA)
Output Supply for ADC (~ 28 mA)
Supply for Support Logic and DAC (~350 mA)
Optional External Reference Input
Supply for Clock Buffer/Optional XTAL
Supply for Optional Amp
PRELIMINARY TECHNICAL DATA
-14-
> 0.5 V p-p. Power to the EL16 is set at jumper E47. E47–E45
powers the buffer from AVDD, E47–E46 powers the buffer from
VCLK/V_XTAL.
Voltage Reference
The AD9430 has an internal 1.23 V voltage reference. The
ADC uses the internal reference as the default when jumpers
E24–E27 and E25–E26 are left open. The full scale can be
increased by placing optional resistor R3. The required value
would vary with process and needs to be tuned for the specific
application. Full scale can similarly be reduced by placing R4;
tuning would be required here as well. An external reference can
be used by shorting the SENSE pin to 3.3 V (place jumper
E26–E25). E27–E24 jumper connects the ADC VREF pin to
EXT_VREF pin at the power connector.
Data Format Select
Data Format Select sets the output data format of the ADC. Set-
ting DFS (E1–E2) low sets the output format to be offset binary;
setting DFS high (E1–E3) sets the output to two’s complement.
I/P
Output timing is set at E11–E13. E12–E11 sets S4 low for
parallel output timing mode. E11–E13 sets S4 high for interleaved
timing mode.
Timing Controls
Flexibility in latch clocking and output timing is accomplished
by allowing for clock inversion at the timing controls section of
the PCB. Each buffered clock is buffered by an XOR and can be
inverted by moving the appropriate jumper for that clock.
Data Outputs
The ADC digital outputs are latched on the board by four LVT574s;
the latch outputs are available at the two 40-pin connectors at pins
11–33 on P23 (channel A) and pins 11–33 on P3 (channel B).
The latch output clocks (data ready) are available at Pin 37 on
P23 (channel A) and Pin 37 on P3 (channel B). The data ready
clocks can be inverted at the timing controls section if needed.
1
2
CH1
2.00V
CH2
2.00V
M 5.00nS
C1 FREQ
84.65608MHz
4/01/2002 REV. PrG
: 4.6nS
CH2