AD9116-EBZ Analog Devices, AD9116-EBZ Datasheet - Page 37

• Manufacturer Part Number: AD9116-EBZ
• Description: Dual, 8-/10-/12-/14-bit Low Power Digital-to-analog Converters
• Manufacturer: Analog Devices

DB[13:0]
DB[13:0]
DIGITAL INTERFACE OPERATION
Digital data for the I and Q DACs is supplied over a single
parallel bus (DB[MSB:0]) accompanied by a qualifying clock
(DCLKIO). The I and Q data is provided to the chip in an
interleaved double data rate (DDR) format. The maximum
guaranteed data rate is 250 MSPS with a 125 MHz clock. The
order of data pairing and the sampling edge selection is user
programmable using the IFIRST and IRISING configuration
bits, resulting in four possible timing diagrams. These are
shown in Figure 76, Figure 77, Figure 78, and Figure 79.
DCLKIO
Q DATA
DCLKIO
Q DATA
I DATA
I DATA
Z
Z
Figure 76. Timing Diagram with IFIRST = 0, IRISING = 0
Figure 77. Timing Diagram with IFIRST = 0, IRISING = 1
A
A
B
B
Y
X
Z
Y
C
C
D
D
A
B
A
Z
E
E
F
F
D
C
C
B
G
G
H
H
E
E
D
F
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DB[13:0]
DB[13:0]
Ideally, the rising and falling edges of the clock fall in the center
of the keep-in-window formed by the set-up and hold times, t
and t
timing diagram is shown in Figure 80.
In addition to the different timing modes listed in Table 2, the
input data can also be presented to the device in either unsigned
binary or twos complement format. The format type is chosen
via the TWOS configuration bit.
DCLKIO
Q DATA
DCLKIO
Q DATA
I DATA
I DATA
H
. Refer to Table 2 for set-up and hold times. A detailed
Z
Z
Figure 78. Timing Diagram with IFIRST = 1, IRISING = 0
Figure 79. Timing Diagram with IFIRST = 1, IRISING = 1
DB[13:0]
DCLKIO
Figure 80. Set-Up and Hold Times for All Input Modes
AD9114/AD9115/AD9116/AD9117
A
A
B
B
A
Y
Z
Z
t
S
C
C
t
H
D
D
B
C
A
B
t
S
t
E
E
H
F
F
D
C
D
E
G
G
H
H
G
E
F
F
S