CY37032VP Cypress Semiconductor Corp., CY37032VP Datasheet - Page 19

• Manufacturer Part Number: CY37032VP
• Description: 5V, 3.3V, Isr High-performance CPLDS
• Manufacturer: Cypress Semiconductor Corp.

Switching Characteristics
Document #: 38-03007 Rev. **
Combinatorial Mode Parameters
t
t
t
t
t
Input Register Parameters
t
t
t
t
t
t
Synchronous Clocking Parameters
t
t
t
t
t
t
t
Product Term Clocking Parameters
t
t
t
t
t
t
Pipelined Mode Parameters
t
Notes:
11. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
12. Logic Blocks operating in Low-Power Mode, add t
13. Outputs using Slow Output Slew Rate, add t
14. When V
PD
PDL
PDLL
EA
ER
WL
WH
IS
IH
ICO
ICOL
CO
S
H
CO2
SCS
SL
HL
COPT
SPT
HPT
ISPT
IHPT
CO2PT
ICS
[12]
[12]
[12, 13, 14]
[12, 13, 14]
[10, 12]
[13, 14]
[12]
[12, 13, 14]
Parameter
[12, 13, 14]
[12, 13, 14]
[12]
[12]
[12, 13, 14]
[12, 13, 14]
[12, 13, 14]
[12, 13, 14]
CCO
= 3.3V, add t
Input to Combinatorial Output
Input to Output Through Transparent Input or Output Latch
Input to Output Through Transparent Input and Output Latches
Input to Output Enable
Input to Output Disable
Clock or Latch Enable Input LOW Time
Clock or Latch Enable Input HIGH Time
Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to Combinatorial Output
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
Synchronous Clock (CLK
Set-Up Time from Input to Sync. Clk (CLK
Register or Latch Data Hold Time
Output Synchronous Clock (CLK
Delay (Through Logic Array)
Output Synchronous Clock (CLK
Clock (CLK
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK
CLK
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK
CLK
Product Term Clock or Latch Enable (PTCLK) to Output
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)
Register or Latch Data Hold Time
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK)
Buried Register Used as an Input Register or Latch Data Hold Time
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)
Input Register Synchronous Clock (CLK
Clock (CLK
3.3IO
1
1
, CLK
, CLK
to this spec.
2
2
0
0
Over the Operating Range
, or CLK
, or CLK
, CLK
, CLK
SLEW
1
1
, CLK
, CLK
3
3
) or Latch Enable
) or Latch Enable
LP
to this spec.
to this spec.
2
2
0
, or CLK
, or CLK
, CLK
1
0
0
, CLK
, CLK
, CLK
3
3
) or Latch Enable (Through Logic Array)
)
[11]
2
1
1
[8]
0
[8]
, or CLK
, CLK
, CLK
, CLK
Description
0
, CLK
2
2
1
, or CLK
, or CLK
, CLK
3
1
) or Latch Enable to Output
, CLK
2
, or CLK
3
3
2
) or Latch Enable to Combinatorial Output
) or Latch Enable to Output Synchronous
, or CLK
Ultra37000™ CPLD Family
3
) to Output Register Synchronous
3
) or Latch Enable
Page 19 of 67
0
0
,
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns