AD9772EB Analog Devices, AD9772EB Datasheet - Page 4

• Manufacturer Part Number: AD9772EB
• Description: 14-Bit/ 160 MSPS TxDAC+ with 2x Interpolation Filter
• Manufacturer: Analog Devices

DIGITAL SPECIFICATIONS
AD9772–SPECIFICATIONS
Parameter
DIGITAL INPUTS
CLOCK INPUTS
PLL CLOCK ENABLED—FIGURE 1a
PLL CLOCK DISABLED—FIGURE 1b
NOTES
1
Specifications subject to change without notice.
Figure 1a. Timing Diagram—PLL Clock Multiplier Enabled
MOD1 and MOD0 have typical input currents of 120 A while SLEEP has a typical input current of 15 A.
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Voltage Range
Common-Mode Voltage
Differential Voltage
Input Setup Time (t
Input Hold Time (t
Latch Pulsewidth (t
Input Setup Time (t
Input Hold Time (t
Latch Pulsewidth (t
CLK/PLLLOCK Delay (t
CLK+ – CLK–
DB0–DB13
IOUTA
IOUTB
OR
1
H
H
LPW
LPW
S
S
t
)
)
S
)
)
)
)
OD
t
PD
t
LPW
t
)
H
0.025%
t
ST
(T
otherwise noted)
MIN
to T
MAX
, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = +0 V, DVDD = +3 V, I
0.025%
–4–
Min
2.1
–10
–10
0
0.75
0.5
1.0
2.5
1.5
1.0
2.5
1.5
Figure 1b. Timing Diagram—PLL Clock Multiplier Disabled
CLK+ – CLK–
PLLLOCK
DB0–DB13
IOUTA
IOUTB
OR
Typ
3
0
5
1.5
1.5
5
t
S
t
OD
Max
0.9
+10
+10
3
2.25
t
PD
t
t
LPW
H
0.025%
t
ST
OUTFS
= 20 mA, unless
Units
V
V
pF
V
V
V
ns
ns
ns
ns
ns
ns
ns
A
A
0.025%
REV. 0